INTERCONNECTION MATRIX USING SEMICONDUCTOR NON-VOLATILE MEMORY

• US 20140140139A1
• Filed: 11/21/2012
• Published: 05/22/2014
• Est. Priority Date: 11/21/2012
• Status: Active Grant

• Current Assignee: Flashsilicon, Incorporation
• Original Assignee: Flashsilicon, Incorporation
• Inventors: WANG, Lee
• Granted Patent: US 8,879,323 B2
• Time in Patent Office: Days
• US Class Current: 365/185.18
• CPC Class Codes: G11C 16/0441 comprising cells containing multiple floating gate devices, e.g. separate read-and-write FAMOS transistors with connected floating gates
• CPC Class Codes: G11C 16/0483 comprising cells having several storage transistors connected in series
• CPC Class Codes: G11C 16/10 Programming or data input circuits
• CPC Class Codes: G11C 16/3418 Disturbance prevention or evaluation; Refreshing of disturbed memory data

Abstract

An interconnection matrix consists of a plurality of semiconductor Non-Volatile Memory (NVM) forming an M×N array. Semiconductor NVM devices in the array are either programmed to a high threshold voltage state or erased to a low threshold voltage state according to a specific interconnection configuration. Applied with a gate voltage bias higher than the low threshold voltage and lower than the high threshold voltage to the control gates of the entire semiconductor NVM devices in the array, the configured interconnection network is formed. The disclosed interconnection matrix can be applied to configuring circuit routing in Integrated Circuit (IC).

Claims

1. A multiple-time programmable interconnection matrix, comprising:

a plurality of non-volatile memory (NVM) cells organized in rows and columns, each NVM cell having a source, a drain, a floating gate, a control gate and a channel region, the control gates of the NVM cells in a row forming a corresponding control gate line, the drains of the NVM cells in a column forming a corresponding bit line, the NVM cells in a row being arranged in cell pairs, such that each of the cell pairs share a common source and are connected to two adjacent bit lines, the common sources of the NVM cells in a row forming a corresponding source line, the NVM cells being configured into a plurality of erased cells and a plurality of programmed cells after each programming cycle;

a plurality of first switches and second switches respectively disposed at first terminals and second terminals of the bit lines; and

a plurality of third switches and fourth switches respectively disposed at first terminals and second terminals of the source lines;

wherein conductivity states of the erased cells and the programmed cells depend on a conductivity type of the NVM cells when the control gate lines are biased.

2. The multiple-time programmable interconnection matrix according to claim 1, wherein the first switches are configured to connect the bit lines to a plurality of first external bus lines in response to a first control signal, wherein the second switches are configured to connect the bit lines to a plurality of second external bus lines in response to a second control signal, wherein the third switches are configured to connect the source lines to a plurality of third external bus lines in response to a third control signal, and wherein the fourth switches are configured to connect the source lines to a plurality of fourth external bus lines in response to a fourth control signal.

3. The multiple-time programmable interconnection matrix according to claim 2, wherein the first switches, the second switches, the third switches and the fourth switches are metal-oxide-semiconductor field-effect transistors (MOSFETs).

4. The multiple-time programmable interconnection matrix according to claim 1, wherein the erased cells with a first threshold voltage are turned on and the programmed cells with a second threshold voltage are turned off when the NVM cells are N-type and each control gate line is biased with a first gate voltage greater than the first threshold voltage and less than the second threshold voltage.

5. The multiple-time programmable interconnection matrix according to claim 4, wherein a selected source line is detached from all the bit lines when a second gate voltage is applied to its corresponding control gate line, and wherein the second gate voltage is lower than the first threshold voltage.

6. The multiple-time programmable interconnection matrix according to claim 4, wherein a selected source line is disconnected from a selected bit line when a corresponding NVM cell is in a programmed state.

7. The multiple-time programmable interconnection matrix according to claim 1, wherein the erased cells are turned off and the programmed cells are turned on when the NVM cells are P-type and all the control gate lines and a well electrode are biased with an operating voltage.

8. The multiple-time programmable interconnection matrix according to claim 7, wherein a selected source line is detached from the bit lines when a gate voltage greater than the operating voltage is applied to its corresponding control gate line.

9. The multiple-time programmable interconnection matrix according to claim 7, wherein a selected source line is connected to a selected bit line when a corresponding NVM cell is in a programmed state.

10. A method of configuring a multiple-time programmable interconnection matrix, the multiple-time programmable interconnection matrix comprising a plurality of non-volatile memory (NVM) cells organized in rows and columns, a plurality of first switches, a plurality of second switches, a plurality of third switches and a plurality of fourth switches, each NVM cell having a source, a drain, a floating gate, a control gate and a channel region, the control gates of the NVM cells in a row forming a corresponding control gate line, the drains of the NVM cells in a column forming a corresponding bit line, the NVM cells in a row being arranged in cell pairs, such that each of the cell pairs share a common source and are connected to two adjacent bit lines, the common sources of the NVM cells in a row forming a corresponding source line, the first switches and the second switches being respectively disposed at first terminals and second terminals of the bit lines, the third switches and the fourth switches being respectively disposed at first terminals and second terminals of the source lines, the method comprising:

changing threshold voltages of the NVM cells to an erased state with a first threshold voltage;

maintaining a plurality of first NVM cells of a row in the erased state with the first threshold voltage for a programming interval by applying an operating voltage to their corresponding bit lines or floating the corresponding bit lines;

programming a plurality of second NVM cells in the row to a programmed state with a second threshold voltage by applying the operating voltage to a corresponding source line, a first high voltage to their corresponding bit lines and a second high voltage to a corresponding control gate line for the programming interval; and

repeating the steps of programming and maintaining on a row by row basis until all the NVM cells are processed;

wherein the first high voltage and the second high voltage are greater than the operating voltage; and

wherein the NVM cells are N-type and the first threshold voltage is less than the second threshold voltage.

11. The method according to claim 10, further comprising:

connecting the bit lines to a plurality of first external bus lines by turning on the first switches in response to a first control signal after the step of repeating;

connecting the bit lines to a plurality of second external bus lines by turning on the second switches in response to a second control signal after the step of repeating;

connecting the source lines to a plurality of third external bus lines by turning on the third switches in response to a third control signal after the step of repeating; and

connecting the source lines to a plurality of fourth external bus lines by turning on the fourth switches in response to a fourth control signal after the step of repeating.

12. The method according to claim 10, further comprising:

connecting the source lines to the bit lines by applying a gate voltage greater than the first threshold voltage to all the control gate lines after the step of changing and before the steps of programming and maintaining.

13. The method according to claim 10, further comprising:

turning off the second NVM cells with the second threshold voltage and turning on the first NVM cells with the first threshold voltage by applying a gate voltage to all the control gate lines after the step of repeating;

wherein the gate voltage is greater than the first threshold voltage and less than the second threshold voltage.

14. The method according to claim 13, wherein (V_thL+V_DD)<

V_a<

V_thH, and wherein W_thL denotes the first threshold voltage, V_thH denotes the second threshold voltage, V_DD denotes the operating voltage and V_a denotes the gate voltage.

15. The method according to claim 13, which operates like a fuse-blown operation in a conventional interconnection matrix having fuse-type elements.

16. The method according to claim 10, further comprising:

detaching a selected source line from the bit lines by applying a gate voltage to a corresponding control gate line to turn off corresponding NVM cells after the step of repeating;

wherein the gate voltage is lower than the first threshold voltage.

17. A method of configuring a multiple-time programmable interconnection matrix, the multiple-time programmable interconnection matrix comprising a plurality of non-volatile memory (NVM) cells organized in rows and columns, a plurality of first switches, a plurality of second switches, a plurality of third switches and a plurality of fourth switches, each NVM cell having a source, a drain, a floating gate, a control gate and a channel region, the control gates of the NVM cells in a row forming a corresponding control gate line, the drains of the NVM cells in a column forming a corresponding bit line, the NVM cells in a row being arranged in cell pairs, such that each of the cell pairs share a common source and are connected to two adjacent bit lines, the common sources of the NVM cells in a row forming a corresponding source line, the first switches and the second switches being respectively disposed at first terminals and second terminals of the bit lines, the third switches and the fourth switches being respectively disposed at first terminals and second terminals of the source lines, the method comprising:

changing threshold voltages of the NVM cells to an erased state with a first threshold voltage;

maintaining a plurality of first NVM cells of a row in the erased state with the first threshold voltage for a programming interval by floating their corresponding bit lines or applying a first high voltage to their corresponding bit lines;

programming a plurality of second NVM cells in the row to a programmed state with a second threshold voltage by applying the first high voltage to both a well electrode and a corresponding source line and a ground voltage to their corresponding bit lines for the programming interval; and

repeating the steps of programming and maintaining on a row by row basis until all the NVM cells are processed;

wherein the NVM cells are P-type and the first threshold voltage is less than the second threshold voltage.

18. The method according to claim 17, further comprising:

connecting the bit lines to a plurality of first external bus lines by turning on the first switches in response to a first control signal after the step of repeating;

connecting the bit lines to a plurality of second external bus lines by turning on the second switches in response to a second control signal after the step of repeating;

connecting the source lines to a plurality of third external bus lines by turning on the third switches in response to a third control signal after the step of repeating; and

connecting the source lines to a plurality of fourth external bus lines by turning on the fourth switches in response to a fourth control signal after the step of repeating.

19. The method according to claim 17, further comprising:

disconnecting all the source lines from all the bit lines by applying a same voltage to the well electrode and all the control gate lines after the step of changing and before the steps of programming and maintaining.

20. The method according to claim 17, further comprising:

turning off the first NVM cells with the first threshold voltage and turning on the second NVM cells with the second threshold voltage by applying an operating voltage to the well electrode and all the control gate lines after the step of repeating.

21. The method according to claim 20, which operates like a fuse-connecting operation in a conventional interconnection matrix having antifuse-type elements.

22. The method according to claim 17, further comprising:

detaching a selected source line from the bit lines by applying a second high voltage to a corresponding control gate line to turn off corresponding NVM cells after the step of repeating;

wherein the second high voltage is greater than an operating voltage.

23. The method according to claim 17, further comprising:

maintaining a plurality of third NVM cells of the other rows in their states by floating their corresponding source lines for the programming interval.