INTERCONNECTION MATRIX USING SEMICONDUCTOR NON-VOLATILE MEMORY
First Claim
1. A multiple-time programmable interconnection matrix, comprising:
- a plurality of non-volatile memory (NVM) cells organized in rows and columns, each NVM cell having a source, a drain, a floating gate, a control gate and a channel region, the control gates of the NVM cells in a row forming a corresponding control gate line, the drains of the NVM cells in a column forming a corresponding bit line, the NVM cells in a row being arranged in cell pairs, such that each of the cell pairs share a common source and are connected to two adjacent bit lines, the common sources of the NVM cells in a row forming a corresponding source line, the NVM cells being configured into a plurality of erased cells and a plurality of programmed cells after each programming cycle;
a plurality of first switches and second switches respectively disposed at first terminals and second terminals of the bit lines; and
a plurality of third switches and fourth switches respectively disposed at first terminals and second terminals of the source lines;
wherein conductivity states of the erased cells and the programmed cells depend on a conductivity type of the NVM cells when the control gate lines are biased.
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Accused Products
Abstract
An interconnection matrix consists of a plurality of semiconductor Non-Volatile Memory (NVM) forming an M×N array. Semiconductor NVM devices in the array are either programmed to a high threshold voltage state or erased to a low threshold voltage state according to a specific interconnection configuration. Applied with a gate voltage bias higher than the low threshold voltage and lower than the high threshold voltage to the control gates of the entire semiconductor NVM devices in the array, the configured interconnection network is formed. The disclosed interconnection matrix can be applied to configuring circuit routing in Integrated Circuit (IC).
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Citations
23 Claims
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1. A multiple-time programmable interconnection matrix, comprising:
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a plurality of non-volatile memory (NVM) cells organized in rows and columns, each NVM cell having a source, a drain, a floating gate, a control gate and a channel region, the control gates of the NVM cells in a row forming a corresponding control gate line, the drains of the NVM cells in a column forming a corresponding bit line, the NVM cells in a row being arranged in cell pairs, such that each of the cell pairs share a common source and are connected to two adjacent bit lines, the common sources of the NVM cells in a row forming a corresponding source line, the NVM cells being configured into a plurality of erased cells and a plurality of programmed cells after each programming cycle; a plurality of first switches and second switches respectively disposed at first terminals and second terminals of the bit lines; and a plurality of third switches and fourth switches respectively disposed at first terminals and second terminals of the source lines; wherein conductivity states of the erased cells and the programmed cells depend on a conductivity type of the NVM cells when the control gate lines are biased. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9)
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10. A method of configuring a multiple-time programmable interconnection matrix, the multiple-time programmable interconnection matrix comprising a plurality of non-volatile memory (NVM) cells organized in rows and columns, a plurality of first switches, a plurality of second switches, a plurality of third switches and a plurality of fourth switches, each NVM cell having a source, a drain, a floating gate, a control gate and a channel region, the control gates of the NVM cells in a row forming a corresponding control gate line, the drains of the NVM cells in a column forming a corresponding bit line, the NVM cells in a row being arranged in cell pairs, such that each of the cell pairs share a common source and are connected to two adjacent bit lines, the common sources of the NVM cells in a row forming a corresponding source line, the first switches and the second switches being respectively disposed at first terminals and second terminals of the bit lines, the third switches and the fourth switches being respectively disposed at first terminals and second terminals of the source lines, the method comprising:
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changing threshold voltages of the NVM cells to an erased state with a first threshold voltage; maintaining a plurality of first NVM cells of a row in the erased state with the first threshold voltage for a programming interval by applying an operating voltage to their corresponding bit lines or floating the corresponding bit lines; programming a plurality of second NVM cells in the row to a programmed state with a second threshold voltage by applying the operating voltage to a corresponding source line, a first high voltage to their corresponding bit lines and a second high voltage to a corresponding control gate line for the programming interval; and repeating the steps of programming and maintaining on a row by row basis until all the NVM cells are processed; wherein the first high voltage and the second high voltage are greater than the operating voltage; and wherein the NVM cells are N-type and the first threshold voltage is less than the second threshold voltage. - View Dependent Claims (11, 12, 13, 14, 15, 16)
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17. A method of configuring a multiple-time programmable interconnection matrix, the multiple-time programmable interconnection matrix comprising a plurality of non-volatile memory (NVM) cells organized in rows and columns, a plurality of first switches, a plurality of second switches, a plurality of third switches and a plurality of fourth switches, each NVM cell having a source, a drain, a floating gate, a control gate and a channel region, the control gates of the NVM cells in a row forming a corresponding control gate line, the drains of the NVM cells in a column forming a corresponding bit line, the NVM cells in a row being arranged in cell pairs, such that each of the cell pairs share a common source and are connected to two adjacent bit lines, the common sources of the NVM cells in a row forming a corresponding source line, the first switches and the second switches being respectively disposed at first terminals and second terminals of the bit lines, the third switches and the fourth switches being respectively disposed at first terminals and second terminals of the source lines, the method comprising:
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changing threshold voltages of the NVM cells to an erased state with a first threshold voltage; maintaining a plurality of first NVM cells of a row in the erased state with the first threshold voltage for a programming interval by floating their corresponding bit lines or applying a first high voltage to their corresponding bit lines; programming a plurality of second NVM cells in the row to a programmed state with a second threshold voltage by applying the first high voltage to both a well electrode and a corresponding source line and a ground voltage to their corresponding bit lines for the programming interval; and repeating the steps of programming and maintaining on a row by row basis until all the NVM cells are processed; wherein the NVM cells are P-type and the first threshold voltage is less than the second threshold voltage. - View Dependent Claims (18, 19, 20, 21, 22, 23)
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Specification