RANDOM NUMBER GENERATING CIRCUIT

• US 20140143292A1
• Filed: 11/21/2013
• Published: 05/22/2014
• Est. Priority Date: 11/21/2012
• Status: Active Grant

• Current Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Original Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Inventors: YASUDA, Shinichi, Tanamoto, Tetsufumi, Inoue, Noriko, Shimbo, Atsushi, Tomita, Akira, Murakami, Ryusuke
• Granted Patent: US 9,547,475 B2
• Time in Patent Office: Days
• US Class Current: 708/251
• CPC Class Codes: G06F 7/58 Random or pseudo-random number generators
• CPC Class Codes: G06F 7/582 Pseudo-random number generators
• CPC Class Codes: G06F 7/584 using finite field arithmetic, e.g. using a linear feedback shift register
• CPC Class Codes: G06F 7/588 Random number generators, i.e. based on natural stochastic processes

Abstract

According to one embodiment, a random number generating circuit includes first to N-th oscillating circuits (N is a natural number equal to 2 or greater), first to N-th latch circuits that latch outputs of the first to N-th oscillating circuits by a first clock having a first frequency, first to N-th exclusive OR circuits, (N+1)-th to (2×N)-th latch circuits that latch outputs of the first to N-th exclusive OR circuits by the first clock, an (N+1)-th exclusive OR circuit that outputs an exclusive OR of outputs of the (N+1)-th to (2×N)-th latch circuits, and an M-bit shift register that converts serial data output from the (N+1)-th exclusive OR circuit into M-bit parallel data (M is a natural number equal to 2 or greater) by a second clock having a second frequency.

Claims

1. A random number generating circuit comprising:

first to N-th oscillating circuits (N is a natural number equal to 2 or greater);

first to N-th latch circuits that latch outputs of the first to N-th oscillating circuits by a first clock having a first frequency;

first to N-th exclusive OR circuits;

(N+1)-th to (2×

N)-th latch circuits that latch outputs of the first to N-th exclusive OR circuits by the first clock;

an (N+1)-th exclusive OR circuit that outputs an exclusive OR of outputs of the (N+1)-th to (2×

N)-th latch circuits; and

an M-bit shift register that converts serial data output from the (N+1)-th exclusive OR circuit into M-bit parallel data (M is a natural number equal to 2 or greater) by a second clock having a second frequency,

wherein the output of the i-th exclusive OR circuit is the exclusive OR of i-th feedback output of a subsequent circuit of the first to N-th exclusive OR circuits and the output of the i-th latch circuit (i is one of 1 to N) and

the second frequency is equal to or lower than the first frequency.

2. The circuit of claim 1,

wherein the i-th feedback output is the output of the (N+i)-th latch circuit (i is one of 1 to N).

3. The circuit of claim 1,

wherein the i-th feedback output is the output of the (N+i+1)-th latch circuit (i is one of 1 to N−

1) and

the N-th feedback output is the output of the (N+1)-th latch circuit.

4. The circuit of claim 1, further comprising:

a frequency divider that divides a frequency of the first clock by X (X is a natural number),

wherein the second clock is output from the frequency divider.

5. The circuit of claim 4,

wherein the frequency divider selectively outputs one of the first clock and a clock obtained by dividing the first clock by X′

(X′

is a natural number equal to 2 or greater) as the second clock.

6. The circuit of claim 4, further comprising:

first to N-th shift registers that monitor outputs of the first to N-th latch circuits,

wherein the X is determined based on outputs of the first to N-th shift registers.

7. The circuit of claim 1,

wherein each of the first to N-th oscillating circuits

includes a NOR circuit into which a first control signal is input and an exclusive OR circuit into which a second control signal and the output of the NOR circuit are input and which outputs an oscillating signal and

the oscillating signal is input into the NOR circuit as a feedback signal.

8. The circuit of claim 1, further comprising:

M multiplexers capable of selecting one of M bits from the M-bit shift register by an output selection signal,

wherein the first and second frequencies are equal and

the M bits from the M multiplexers are used as an entropy source.

9. The circuit of claim 1, further comprising:

an entropy measuring circuit that measures entropy based on outputs of the first to N-th latch circuits; and

a clock control circuit that generates the second clock based on the entropy measured by the entropy measuring circuit.

10. The circuit of claim 1,

wherein a value of the N is an odd number.

11. A random number generating circuit comprising:

first to N-th oscillating circuits (N is a natural number equal to 2 or greater);

first to N-th latch circuits that latch outputs of the first to N-th oscillating circuits by a first clock having a first frequency;

a first exclusive OR circuit that outputs an exclusive OR of outputs of the first to N-th latch circuits;

a second exclusive OR circuit;

an (N+1)-th latch circuit that latches the output of the second exclusive OR circuit by the first clock; and

an M-bit shift register that converts serial data output from the (N+1)-th latch circuit into M-bit parallel data (M is a natural number equal to 2 or greater) by a second clock having a second frequency,

wherein the output of the second exclusive OR circuit is the exclusive OR of the output of the first exclusive OR circuit and the output of the (N+1)-th latch circuit and

the second frequency is equal to or lower than the first frequency.

12. The circuit of claim 11, further comprising:

a frequency divider that divides a frequency of the first clock by X (X is a natural number),

wherein the second clock is output from the frequency divider.

13. The circuit of claim 12,

wherein the frequency divider selectively outputs one of the first clock and a clock obtained by dividing the first clock by X′

(X′

is a natural number equal to 2 or greater) as the second clock.

14. The circuit of claim 12, further comprising:

first to N-th shift registers that monitor outputs of the first to N-th latch circuits,

wherein the X is determined based on outputs of the first to N-th shift registers.

15. The circuit of claim 11,

wherein each of the first to N-th oscillating circuits

includes a NOR circuit into which a first control signal is input and an exclusive OR circuit into which a second control signal and the output of the NOR circuit are input and which outputs an oscillating signal and

the oscillating signal is input into the NOR circuit as a feedback signal.

16. The circuit of claim 11, further comprising:

M multiplexers capable of selecting one of M bits from the M-bit shift register by an output selection signal,

wherein the first and second frequencies are equal and

the M bits from the M multiplexers are used as an entropy source.

17. The circuit of claim 11, further comprising:

an entropy measuring circuit that measures entropy based on outputs of the first to N-th latch circuits; and

a clock control circuit that generates the second clock based on the entropy measured by the entropy measuring circuit.

18. The circuit of claim 11,

wherein a value of the N is an odd number.