RANDOM NUMBER GENERATING CIRCUIT
First Claim
1. A random number generating circuit comprising:
- first to N-th oscillating circuits (N is a natural number equal to 2 or greater);
first to N-th latch circuits that latch outputs of the first to N-th oscillating circuits by a first clock having a first frequency;
first to N-th exclusive OR circuits;
(N+1)-th to (2×
N)-th latch circuits that latch outputs of the first to N-th exclusive OR circuits by the first clock;
an (N+1)-th exclusive OR circuit that outputs an exclusive OR of outputs of the (N+1)-th to (2×
N)-th latch circuits; and
an M-bit shift register that converts serial data output from the (N+1)-th exclusive OR circuit into M-bit parallel data (M is a natural number equal to 2 or greater) by a second clock having a second frequency,wherein the output of the i-th exclusive OR circuit is the exclusive OR of i-th feedback output of a subsequent circuit of the first to N-th exclusive OR circuits and the output of the i-th latch circuit (i is one of 1 to N) andthe second frequency is equal to or lower than the first frequency.
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Accused Products
Abstract
According to one embodiment, a random number generating circuit includes first to N-th oscillating circuits (N is a natural number equal to 2 or greater), first to N-th latch circuits that latch outputs of the first to N-th oscillating circuits by a first clock having a first frequency, first to N-th exclusive OR circuits, (N+1)-th to (2×N)-th latch circuits that latch outputs of the first to N-th exclusive OR circuits by the first clock, an (N+1)-th exclusive OR circuit that outputs an exclusive OR of outputs of the (N+1)-th to (2×N)-th latch circuits, and an M-bit shift register that converts serial data output from the (N+1)-th exclusive OR circuit into M-bit parallel data (M is a natural number equal to 2 or greater) by a second clock having a second frequency.
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Citations
18 Claims
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1. A random number generating circuit comprising:
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first to N-th oscillating circuits (N is a natural number equal to 2 or greater); first to N-th latch circuits that latch outputs of the first to N-th oscillating circuits by a first clock having a first frequency; first to N-th exclusive OR circuits; (N+1)-th to (2×
N)-th latch circuits that latch outputs of the first to N-th exclusive OR circuits by the first clock;an (N+1)-th exclusive OR circuit that outputs an exclusive OR of outputs of the (N+1)-th to (2×
N)-th latch circuits; andan M-bit shift register that converts serial data output from the (N+1)-th exclusive OR circuit into M-bit parallel data (M is a natural number equal to 2 or greater) by a second clock having a second frequency, wherein the output of the i-th exclusive OR circuit is the exclusive OR of i-th feedback output of a subsequent circuit of the first to N-th exclusive OR circuits and the output of the i-th latch circuit (i is one of 1 to N) and the second frequency is equal to or lower than the first frequency. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10)
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11. A random number generating circuit comprising:
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first to N-th oscillating circuits (N is a natural number equal to 2 or greater); first to N-th latch circuits that latch outputs of the first to N-th oscillating circuits by a first clock having a first frequency; a first exclusive OR circuit that outputs an exclusive OR of outputs of the first to N-th latch circuits; a second exclusive OR circuit; an (N+1)-th latch circuit that latches the output of the second exclusive OR circuit by the first clock; and an M-bit shift register that converts serial data output from the (N+1)-th latch circuit into M-bit parallel data (M is a natural number equal to 2 or greater) by a second clock having a second frequency, wherein the output of the second exclusive OR circuit is the exclusive OR of the output of the first exclusive OR circuit and the output of the (N+1)-th latch circuit and the second frequency is equal to or lower than the first frequency. - View Dependent Claims (12, 13, 14, 15, 16, 17, 18)
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Specification