FLEXIBLE CONTROL MECHANISM FOR STORE GATHERING IN A WRITE BUFFER

• US 20140143471A1
• Filed: 11/20/2012
• Published: 05/22/2014
• Est. Priority Date: 11/20/2012
• Status: Active Grant

• Current Assignee: NXP USA, Inc. (NXP Semiconductors NV)
• Original Assignee: Freescale Semiconductor, Inc. (NXP Semiconductors NV)
• Inventors: Moyer, William C., Pho, Quyen
• Granted Patent: US 9,158,725 B2
• Time in Patent Office: Days
• US Class Current: 710/310
• CPC Class Codes: G06F 12/04 Addressing variable-length words or parts of words
• CPC Class Codes: G06F 13/4059 where the synchronisation uses buffers, e.g. for speed matching between buses
• CPC Class Codes: G06F 9/30043 LOAD or STORE instructions; Clear instruction
• CPC Class Codes: G06F 9/3824 Operand accessing
• CPC Class Codes: Y02D 10/00 Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

A store gathering policy is enabled or disabled at a data processing device. A store gathering policy to be implemented by a store buffer can be selected from a plurality of store gathering polices. For example, the plurality of store gathering policies can be constrained or unconstrained. A store gathering policy can be enabled by a user programmable storage location. A specific store gathering policy can be specified by a user programmable storage location. A store gathering policy can be determined based upon an attribute of a store request, such as based upon a destination address.

Claims

1. A method comprising:

receiving a first store request at a store buffer;

receiving a second store request at the store buffer;

gathering data information from the first and second store requests in a first entry of the store buffer in response to determining that gathered stores are required to be contiguous once gathered; and

optimizing a write transaction size from the store buffer to a system bus based on a container size determined from the gathered data information in the first entry of the store buffer;

wherein optimizing includes selecting the write transaction size from a set of available transaction sizes, the user programmable indicator indicating the set of available transaction sizes.

2. The method of claim 1 wherein gathering data information from the first and second store requests in the first entry of the store buffer is in response to a cache hit indicator indicating a cache hit.

3. The method of claim 1 wherein selecting the write transaction size selects the a minimum number of contiguous bytes needed for the write transaction that ensures the gathered data information modified pursuant to the first and second store requests is written to the system bus.

4. The method of claim 1 wherein the first and second store requests are non-contiguous store requests.

5. The method of claim 4 wherein optimizing the write transaction size from the store buffer to the system bus comprises selecting a minimum transaction size from the set that is at least equal to the minimum number of contiguous bytes needed for the write transaction to ensure the gathered data information is written to the system bus.

6. The method of claim 1 wherein the container size is determined from stored strobe flags at the first entry of the store buffer.

7. The method of claim 1 wherein optimizing the write transaction size from the store buffer to the system bus is enabled based on a user programmable storage location.

8. A method comprising:

receiving a first store request at a store buffer;

receiving a second store request at the store buffer;

gathering data information of the first and second store requests in a first entry of the store buffer in response to determining a cache hit has occurred for a target address of the first and second store requests; and

optimizing a write transaction size from the store buffer to a system bus based on a container size determined from the gathered data information in the first entry of the store buffer, wherein optimizing includes selecting the write transaction size from a set of available transaction sizes, the user programmable indicator indicating the set of available transaction sizes.

9. The method of claim 8 wherein the selecting the write transaction size selects a minimum number of contiguous bytes needed for the write transaction that ensures the gathered data information modified pursuant to the first and second store requests is written to the system bus.

10. The method of claim 8 wherein the container size is determined from stored strobe flags at the first entry of the store buffer.

11. The method of claim 8 wherein the first and second store requests are non-contiguous store requests.

12. The method of claim 8 wherein optimizing the write transaction size from the store buffer to the system bus comprises selecting a minimum transaction size from the set that is at least equal to the minimum number of contiguous bytes needed for the write transaction to ensure the gathered data information is written to the system bus.

13. The method of claim 12 wherein the minimum size transfer is a halfword.

14. The method of claim 8 wherein optimizing the write transaction size from the store buffer to the system bus is enabled based on a user programmable storage location.

15. A device, comprising:

a data processing core to initiate store requests;

a system bus, coupled to a bus interface unit, to communicate store requests;

a store buffer comprising a store buffer control module to receive a first store request, to receive a second store request, and to gather data information of the first and second store request in a first entry of the store buffer; and

a data cache coupled to the store buffer, wherein the store buffer is to optimizes a write transaction size of a write transaction to the system bus based on a container size determined from the gathered data information in the first entry of the store buffer, wherein optimizing includes selecting the write transaction size from a set of available transaction sizes, the user programmable indicator indicating the set of available transaction sizes.

16. The device of claim 15, wherein selecting the write transaction size selects a minimum number of contiguous bytes needed for the write transaction that ensures the gathered data information modified pursuant to the first and second store requests is written to the system bus.

17. The device of claim 15, wherein in response to a cache hit, the store buffer gathers data information from the first and second store requests wherein the first and second store requests are non-contiguous store requests.

18. The device of claim 15, wherein an external address and the container size is further determined from the stored strobe flags at the first entry of the store buffer.

19. The device of claim 15, wherein available write transaction sizes are indicated by a user programmable indicator.

20. The device of claim 15, wherein the write transaction size optimization from the store buffer to the system bus is enabled based on a user programmable storage location.