THREAD CONSOLIDATION IN PROCESSOR CORES

• US 20140143570A1
• Filed: 08/15/2013
• Published: 05/22/2014
• Est. Priority Date: 11/20/2012
• Status: Active Grant

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: Bose, Pradip, Buyuktosunoglu, Alper, Rosenburg, Bryan S., Ryu, Kyung D., Vega, Augusto J.
• Granted Patent: US 9,141,173 B2
• Time in Patent Office: Days
• US Class Current: 713/323
• CPC Class Codes: G06F 1/324 by lowering clock frequency
• CPC Class Codes: G06F 1/3246 by software initiated power-off
• CPC Class Codes: G06F 1/3287 by switching off individual functional units in the computer system
• CPC Class Codes: G06F 1/3296 by lowering the supply or operating voltage
• CPC Class Codes: Y02D 10/00 Energy efficient computing, e.g. low power processors, power management or thermal management
• CPC Class Codes: Y02D 30/50 in wire-line communication networks, e.g. low power modes or reduced link rate

Abstract

According to one embodiment, a method for thread consolidation is provided for a system that includes an operating system and a multi-core processing chip in communication with an accelerator chip. The method includes running an application having software threads on the operating system, mapping the software threads to physical cores in the multi-core processing chip, identifying one or more idle hardware threads in the multi-core processing chip and identifying one or more idle accelerator units in the accelerator chip. The method also includes executing the software threads on the physical cores and the accelerator unit. The method also includes the controller module consolidating the software threads executing on the physical cores, resulting in one or more idle physical cores and a consolidated physical core. The method also includes the controller module activating a power savings mode for the one or more idle physical cores.

Claims

1. A method for thread consolidation in a system that includes an operating system and a multi-core processing chip in communication with an accelerator chip, the method comprising:

running an application having software threads on the operating system;

mapping the software threads to physical cores in the multi-core processing chip;

identifying one or more idle hardware threads in the multi-core processing chip;

identifying one or more idle accelerator units in the accelerator chip;

executing the software threads on the physical cores and the accelerator unit;

consolidating, by the controller module, the software threads executing on the physical cores, resulting in one or more idle physical cores and a consolidated physical core; and

activating, by the controller module, a power savings mode for the one or more idle physical cores.

2. The method of claim 1, further comprising:

consolidating, by the controller module, the software threads executing on the accelerator units to provide one or more idle accelerator units; and

activating, by the controller module, a power savings mode for the one or more idle accelerator units.

3. The method of claim 1, wherein the accelerator chip comprises an active memory device.

4. The method of claim 1, wherein:

executing the software threads on the physical cores and the accelerator unit further comprises executing parent threads on the physical cores, wherein the parent threads spawn child threads;

mapping one or more of the software threads to the accelerator unit further comprises mapping the child threads to the accelerator unit; and

consolidating the software threads executing on the physical cores further comprises consolidating the parent threads to execute on one of the physical cores to provide the one or more idle physical cores.

5. The method of claim 1, wherein mapping the software threads to physical cores further comprises mapping the software threads to logical cores in the operating system and mapping the logical cores to physical cores in the multi-core processing chip.

6. The method of claim 1, wherein identifying the accelerator unit further comprises identifying an idle hardware thread in the accelerator unit.

7. The method of claim 1, wherein mapping the software threads to physical cores further comprises mapping the software threads to idle hardware threads located in the physical cores.

8. The method of claim 7, wherein mapping the software threads to the accelerator unit further comprises causing a first hardware thread in a first physical core to become idle, the first physical core being one of the physical cores.

9. The method of claim 8, wherein consolidating the software threads further comprises assigning a software thread from a second physical core to execute on the first hardware thread, thus causing the second physical core to become idle and saving power in the multi-core processing chip.

10. The method of claim 1, wherein the multi-core processing chip is a multi-thread enabled chip capable of supporting software threads executing simultaneously in the core.

11. The method of claim 1, wherein identifying the accelerator unit further comprises using information provided by a compiler to determine the one or more of the software threads for mapping to the accelerator unit.