Design, Layout, and Manufacturing Techniques for Multivariant Integrated Circuits

• US 20140143742A1
• Filed: 01/25/2014
• Published: 05/22/2014
• Est. Priority Date: 04/11/2011
• Status: Active Grant

• Current Assignee: NVIDIA Corporation
• Original Assignee: NVIDIA Corporation
• Inventors: Kelleher, Brian
• Granted Patent: US 9,424,383 B2
• Time in Patent Office: Days
• US Class Current: 716/54
• CPC Class Codes: G03F 1/36 Masks having proximity correction features; Preparation thereof, e.g. optical proximity correction [OPC] design processes
• CPC Class Codes: G06F 30/39 Circuit design at the physical level physical level design for reconfigurable circuits G06F30/347
• CPC Class Codes: H01L 27/0207 Geometrical layout of the components, e.g. computer aided design; custom LSI, semi-custom LSI, standard cell technique

Abstract

An integrated circuit (IC) is designed that includes one variant having a plurality of a modular circuits communicatively coupled together and a second variant having a sub-set of the plurality of modular circuits. The modular circuits are then laid out on a wafer for fabricating each of the variants of the IC. The layout includes routing communicative couplings between the sub-set of the modular circuits of the second variant to the other modular circuits of the first variant in one or more metallization layers to be fabricated last. Fabricating the IC is then started, up to but not including the one or more metallization layers to be fabricated last. One or more of the plurality of variants of the IC is selected based upon a demand predicted during fabrication. Fabrication then continues with the last metallization layers of the IC according to the selected layout.

Claims

4-1. The method according to claim 1, further comprising:

analyzing a market to identify one or more attributes selected from a group consisting of one or more product features, one or more performance metrics, one or more target costs, and a demand; and

designing the integrated circuit including the plurality of variants based on the market analysis.

7. A method comprising:

designing a first set of one or more modular circuits and a second set of the one or more modular circuits, wherein the first set of modular circuits are adapted to separately implement a first one of a plurality of selectable integrated circuits and the second set of modular circuits are adapted to separately implement a second one of a plurality of selectable integrated circuits, or the first and second sets of the modular circuits are adapted to combine to implement a third one of a plurality of selectable integrated circuits;

laying out a plurality of instantiations of the first set of one or more modular circuits and the second set of one or more modular circuits, wherein each instantiation of the first and second set of modular integrated circuits are separated from other instantiations by primary scribe boundaries, wherein the first set and second set of the modular circuits of each instantiation are separated by a secondary scribe boundary, and wherein interconnects and vias between the first set and second set of the modular circuits in each instantiation are laid out in one or more metallization layers to be fabricated last;

fabricating the plurality of instantiations of the first set of one or more modular circuits and the second set of one or more modular circuits on a wafer according to the layout up to but not including fabricating the one or more metallization layers including the interconnects and vias between the first set and second set of the modular circuits in each instantiation;

predicting a demand for each of the first, second and third integrated circuits during fabrication of the plurality of instantiations of the first and second sets of modular circuits up to the one or more metallization layers including the interconnects and vias between the first and second sets of the modular circuits in each instantiation;

selectively fabricating the one or more metallization layers including the interconnects and vias between the first set and second set of the modular circuits or not based upon the predicted demand for the first, second and third integrated circuits; and

selectively singulating the wafer into a first plurality of dice each including the first set of one or more modular circuits and a second plurality of dice each including the second set of one or more modular circuits along the primary and secondary scribe boundaries, or into a third plurality of die each including the first and second set of modular integrated circuits and the interconnects and vias along the primary scribe boundaries.

8. The method according to claim 7, further comprising:

estimating a yield for each of the selectable integrated circuits during fabrication of the integrated circuit up to but not including the interconnects and vias;

selectively fabricating the one or more metallization layers including the interconnects and vias between the first set and second set of the modular circuits or not further based upon the estimated yield; and

selectively singulating the wafer into the first plurality of dice each and the second plurality of dice each along the primary and secondary scribe boundaries, or into the third plurality of die along the primary scribe boundaries further based upon the estimated yield.

9. The method according to claim 7, further comprising:

estimating an initial yield for each of the selectable integrated circuits prior to fabricating the plurality of instantiations of the first set of one or more modular circuits and the second set of one or more modular circuits on a wafer up to but not including the one or more metallization layers including the interconnects and vias between the first set and second set of the modular circuits;

designing the first set of one or more modular circuits and the second set of one or more modular circuits based on the initial estimated yield; and

laying out the plurality of instantiations of the first set of one or more modular circuits and the second set of one or more modular circuits based on the initial estimated yield.

10. The method according to claim 7, further comprising:

predicting an initial demand for each of the selectable integrated circuits prior to fabricating the plurality of instantiations of the first set of one or more modular circuits and the second set of one or more modular circuits on a wafer up to but not including the one or more metallization layers including the interconnects and vias between the first set and second set of the modular circuits; and

fabricating the plurality of instantiations of the first set of one or more modular circuits and the second set of one or more modular circuits on a wafer up to but not including the one or more metallization layers including the interconnects and vias between the first set and second set of the modular circuits according to the layout and the initial predicted demand.

11. The method according to claim 7, wherein the first set of one or more modular circuits includes a different number of modular circuits as the second set of one or more modular circuits.

12. The method according to claim 7, wherein the first set of one or more modular circuits includes a same number of modular circuits as the second set of one or more modular circuits.