Automated Circuit Design

• US 20140143743A1
• Filed: 01/27/2014
• Published: 05/22/2014
• Est. Priority Date: 10/04/2004
• Status: Active Grant

• Current Assignee: Synopsys Incorporated
• Original Assignee: Synopsys Incorporated
• Inventors: Tian, Bing, McElvain, Kenneth S.
• Granted Patent: US 9,069,920 B2
• Time in Patent Office: Days
• US Class Current: 716/103
• CPC Class Codes: G06F 30/30 Circuit design
• CPC Class Codes: G06F 30/327 Logic synthesis; Behaviour synthesis, e.g. mapping logic, HDL to netlist, high-level language to RTL or netlist
• CPC Class Codes: G06F 30/394 Routing G06F30/396 takes precedence

Abstract

A method implemented on a data processing system for circuit synthesis is discussed. In one embodiment, the method comprises determining a net of a circuit design, the net driving one or more first loads to use a first type of routing resources and one or more second loads to use a second type of routing resources, and splitting the net into a first net and a second net, the first net driving the one or more first loads, the second net driving the one or more second loads.

Claims

1. A method implemented on a data processing system for circuit synthesis, the method comprising:

determining a net of a circuit design, the net driving one or more first loads to use a first type of routing resources and one or more second loads to use a second type of routing resources; and

splitting the net into a first net and a second net, the first net driving the one or more first loads, the second net driving the one or more second loads.

2. The method of claim 1, wherein said splitting comprises:

replicating a driver element of the net to have a first and second instances of the driver element, the first instance of the driver element driving the first net, the second instance of the driver element driving the second net.

3. The method of claim 1, wherein said splitting comprises:

locating a replication of a driver element of the net; and

configuring the driver element and the replication of the driver to drive the first and second nets separately.

4. The method of claim 1, wherein each of the one or more first loads comprise one or more of:

clock;

reset;

set;

register enable;

or

multiplexer select.

5. The method of claim 4, wherein the first and second types of routing resources of the circuit design is for field programmable gate arrays (FPGA).

6. The method of claim 1, wherein the one or more first loads are control loads and the one or more second loads are non-control loads.

7. A non-transitory machine readable medium containing executable computer program instructions which when executed by a digital processing system cause said system to perform a method for circuit synthesis, the method comprising:

determining a net of a circuit design, the net driving one or more first loads to use a first type of routing resources and one or more second loads to use a second type of routing resources; and

splitting the net into a first net and a second net, the first net driving the one or more first loads, the second net driving the one or more second loads.

8. The medium of claim 7, wherein said splitting comprises:

replicating a driver element of the net to have a first and second instances of the driver element, the first instance of the driver element driving the first net, the second instance of the driver element driving the second net.

9. The medium of claim 7, wherein said splitting comprises:

locating a replication of a driver element of the net; and

configuring the driver element and the replication of the driver to drive the first and second nets separately.

10. The medium of claim 7, wherein each of the one or more first loads comprise one or more of:

clock;

reset;

set;

register enable;

or

multiplexer select.

11. The medium of claim 7, wherein the first and second types of routing resources of the circuit design is for field programmable gate arrays (FPGA).

12. The medium of claim 7, wherein the one or more first loads are control loads and the one or more second loads are non-control loads.

13. A data processing system for circuit synthesis, the data processing system comprising:

a memory; and

a processor coupled to the memory, wherein the processor is configured to determine a net of a circuit design, the net driving one or more first loads to use a first type of routing resources and one or more second loads to use a second type of routing resources; and

the processor configured to

split the net into a first net and a second net, the first net driving the one or more first loads, the second net driving the one or more second loads.

14. The data processing system of claim 13, wherein said processor is further configured to

replicate a driver element of the net to have a first and second instances of the driver element, the first instance of the driver element driving the first net, the second instance of the driver element driving the second net.

15. The data processing system of claim 13, wherein said processor is further configured to

locate a replication of a driver element of the net;

and

configure the driver element and the replication of the driver to drive the first and second nets separately.

16. The data processing system of claim 13, wherein each of the one or more first loads comprises one or more one of:

clock;

reset;

set;

register enable;

or

multiplexer select.

17. The data processing system of claim 13, wherein the first and second types of routing resources of the circuit design is for field programmable gate arrays (FPGA).

18. The data processing system of claim 13, wherein the one or more first loads are control loads and the one or more second loads are non-control loads.

19. A data processing system for circuit synthesis, comprising:

means for determining a net of a circuit design, the net driving one or more first loads to use a first type of routing resources and one or more second loads to use a second type of routing resources; and

means for splitting the net into a first net and a second net, the first net driving the one or more first loads, the second net driving the one or more second loads.

20. The data processing system of claim 19, wherein said means for splitting comprises

means for replicating a driver element of the net to have a first and second instances of the driver element, the first instance of the driver element driving the first net, the second instance of the driver element driving the second net.

21. The data processing system of claim 19, wherein said means for splitting comprises

means for locating a replication of a driver element of the net;

and

means for configuring the driver element and the replication of the driver to drive the first and second nets separately.