APPARATUS AND METHODS FOR ULTRASOUND PROBES

• US 20140144240A1
• Filed: 11/28/2012
• Published: 05/29/2014
• Est. Priority Date: 11/28/2012
• Status: Active Grant

• Current Assignee: Analog Devices, Inc.
• Original Assignee: Analog Devices, Inc.
• Inventors: PETERSEN, Corey D., BARLOW, Allen R., TAYLOR, Gerard E.
• Granted Patent: US 9,479,162 B2
• Time in Patent Office: Days
• US Class Current: 73/632
• CPC Class Codes: B06B 1/0215 for generating pulses, e.g. bursts of oscillations, envelopes
• CPC Class Codes: H03K 17/693 Switching arrangements with several input- or output-terminals, e.g. multiplexers, distributors logic circuits H03K19/00; code converters H03M5/00, H03M7/00
• CPC Class Codes: H03K 2217/0054 Gating switches, e.g. pass gates

Abstract

Apparatus and methods for ultrasound probes are provided. In certain implementations, a receive switch for an ultrasound probe includes a first field effect transistor (FET) and a second FET electrically connected in series between a first terminal and a second terminal with the FETs'"'"' sources connected to one another. The receive switch includes a positive threshold detection and control circuit for turning off the receive switch when a voltage of the first terminal is greater than a positive threshold voltage, and a negative threshold detection and control circuit for turning off the receive switch when the first terminal'"'"'s voltage is less than a negative threshold voltage. The receive switch further includes a gate bias circuit that can bias the gates of the first and second FETs so as to turn on the receive switch when no positive or negative high voltage conditions are detected on the first terminal.

Claims

1. A receive switch comprising:

a first terminal;

a second terminal;

a first field effect transistor (FET) including a drain electrically connected to the first terminal, a gate electrically connected to a gate node, and a source electrically connected to a source node;

a second FET including a drain electrically connected to the second terminal, a source electrically connected to the source node, and a gate electrically connected to the gate node;

a first threshold detection and control circuit configured to detect a voltage of the first terminal and to turn off at least one of the first FET or the second FET when the voltage of the first terminal is greater than a first threshold voltage;

a second threshold detection and control circuit configured to detect the voltage of the first terminal and to turn off at least one of the first FET or the second FET when the voltage of the first terminal is less than a second threshold voltage; and

a gate bias circuit configured to turn on the first and second FETs when neither the first threshold detection and control circuit nor the second threshold detection and control circuit is active to turn off the first or second FETs.

2. The receive switch of claim 1, wherein the first FET and the second FET are n-type field effect transistors, wherein the first threshold detection and control circuit is configured to control a voltage of the gate node to turn off the first and second FETs when the voltage of the first terminal is greater than the first threshold voltage, and wherein the second threshold detection and control circuit is configured to electrically connect the gate node to the source node when the voltage of the first terminal is less than the second threshold voltage.

3. The receive switch of claim 2, wherein the gate bias circuit comprises a third FET and a first resistor electrically connected in series between the gate node and a power high supply.

4. The receive switch of claim 3, further comprising a second resistor and a diode electrically connected in series between the power high supply and a source of the third FET.

5. The receive switch of claim 2, wherein the first threshold detection and control circuit comprises a first diode, a third FET, and a resistor electrically connected in series between the first terminal and a first voltage supply.

6. The receive switch of claim 5, wherein the first diode includes an anode electrically connected to the first terminal and a cathode electrically connected to a drain of the third FET, wherein the resistor includes a first end electrically connected to a source of the third FET and a second end electrically connected to the first voltage supply, and wherein the third FET further includes a gate electrically connected to a second voltage supply.

7. The receive switch of claim 6, further comprising a comparator including an input electrically connected to the first end of the resistor.

8. The receive switch of claim 7, further comprising a second diode and a fourth FET, wherein the second diode includes an anode electrically connected to the gate node and a cathode electrically connected to a drain of the fourth FET, and wherein the fourth FET further includes a source electrically connected to the first voltage supply and a gate electrically connected to an output of the comparator.

9. The receive switch of claim 7, further comprising a Zener diode including a cathode electrically connected to the input of the comparator and an anode electrically connected to the first voltage supply.

10. The receive switch of claim 2, wherein the second threshold detection and control circuit comprises a resistor, a third FET, a fourth FET, and a Zener diode, wherein the Zener diode includes an anode electrically connected to the source node and a cathode electrically connected to a drain of the third FET and to a gate of the fourth FET, wherein the fourth FET includes a source electrically connected to the source node and a drain electrically connected to the gate node, and wherein the resistor includes a first end electrically connected to a source of the third FET and a second end electrically connected to a first voltage supply.

11. The receive switch of claim 1, further comprising a load balancing circuit, wherein the load balancing circuit is configured to balance a first load current and a second load current, wherein the first load current is associated with a voltage on the first terminal that is greater than the first threshold voltage, and wherein the second load current is associated with a voltage on the first terminal that is less than the second threshold voltage.

12. The receive switch of claim 1, further comprising a switch disable circuit configured to activate in response to a control signal, wherein the switch disable circuit is configured to turn off at least one of the first FET or the second FET when the switch disable circuit is activated, and wherein the first threshold detection and control circuit is further configured to deactivate the switch disable circuit when the first threshold detection and control circuit determines that the voltage of the first terminal is greater than the first threshold voltage.

13. The receive switch of claim 1, wherein the first threshold voltage is greater than a ground voltage, and wherein the second threshold voltage is less than the ground voltage.

14. The receive switch of claim 1, wherein the first FET and the second FET are p-type field effect transistors, wherein the first threshold detection and control circuit is configured to electrically connect the gate node to the source node when the voltage of the first terminal is greater than the first threshold voltage, and wherein the second threshold detection and control circuit is configured to control a voltage of the gate node to turn off the first and second FETs when the voltage of the first terminal is less than the second threshold voltage.

15. An ultrasound probe comprising:

a cable port configured to receive a transmit signal over a cable;

a first transducer configured to generate an acoustic signal in response to the transmit signal and to generate a receive signal in response to an echo of the acoustic signal;

a first transmit circuit electrically connected between the first transducer and the cable port, wherein the first transmit circuit is configured to pass the transmit signal and to block the receive signal; and

a first switch protected amplifier comprising;

an amplifier having an input and an output, wherein the amplifier is configured to amplify the receive signal for transmission along the cable;

a first switch comprising a first terminal electrically connected to the first transducer and a second terminal electrically connected to the input of the amplifier, wherein the first switch is configured to automatically switch to an off state when the transmit signal is detected on the first terminal of the first switch; and

a second switch comprising a first terminal electrically connected to the cable port and a second terminal electrically connected to the output of the amplifier, wherein the second switch is configured to automatically switch to an off state when the transmit signal is detected on the first terminal of the second switch.

16. The ultrasound probe of claim 15, further comprising:

a first transmit switch electrically connected in series with the first transmit circuit between the first transducer and the cable port.

17. The ultrasound probe of claim 16, further comprising:

a second transducer;

a second transmit circuit;

a second transmit switch electrically connected in series with the second transmit circuit between the second transducer and the cable port; and

a second switch protected amplifier electrically connected between the second transducer and the second transmit circuit,

wherein the first transmit switch is configured to activate in response to a first select signal so as to provide the transmit signal to the first transducer, and wherein the second transmit switch is configured to activate in response to a second select signal so as to provide the transmit signal to the second transducer.

18. The ultrasound probe of claim 15, wherein the first switch further comprises:

a first field effect transistor (FET) including a drain electrically connected to the first terminal of the first switch, a gate electrically connected to a gate node, and a source electrically connected to a source node;

a second FET including a drain electrically connected to the second terminal, a gate electrically connected to the gate node, and a source electrically connected to the source node.

19. The ultrasound probe of claim 18, wherein the first switch further comprises:

a first threshold detection and control circuit configured to turn off at least one of the first FET or the second FET when a voltage of the first terminal of the first switch is greater than a first threshold voltage;

a second threshold detection and control circuit configured to turn off at least one of the first FET or the second FET when the voltage of the first terminal of the first switch is less than a second threshold voltage; and

a gate bias circuit configured to turn on the first and second FETs when neither the first threshold detection and control circuit nor the second threshold detection and control circuit is active to turn off the first or second FETs.

20. The ultrasound probe of claim 19, wherein the first FET and the second FET are n-type field effect transistors, wherein the first threshold detection and control circuit is configured to control a voltage of the gate node to turn off the first and second FETs when the voltage of the first terminal of the first switch is greater than the first threshold voltage, and wherein the second threshold detection and control circuit is configured to electrically connect the gate node to the source node when the voltage of the first terminal of the first switch is less than the second threshold voltage.

21. The ultrasound probe of claim 19, wherein the first switch further comprises a switch disable circuit configured to activate in response to a control signal, wherein the switch disable circuit is configured to turn off the first switch when the switch disable circuit is activated, and wherein the first threshold detection and control circuit is further configured to deactivate the switch disable circuit when the first threshold detection and control circuit determines that the voltage of the first terminal of the first switch is greater than the first threshold voltage.

22. The ultrasound probe of claim 19, wherein the first switch further comprises a load balancing circuit, wherein the load balancing circuit is configured to balance a first load current and a second load current, wherein the first load current is associated with a voltage on the first terminal that is greater than the first threshold voltage, and wherein the second load current is associated with a voltage on the first terminal that is less than the second threshold voltage.

23. A method of switching in an ultrasound probe, the method comprising:

receiving an ultrasound signal on an input terminal of a receive switch, the receive switch comprising a first field effect transistor (FET) and a second FET, wherein the first FET includes a drain electrically connected to the input terminal, a gate electrically connected to a gate node, and a source electrically connected to a source node, and wherein the second FET includes a drain electrically connected to the output terminal, a source electrically connected to the source node, and a gate electrically connected to the gate node;

comparing a voltage of the input terminal to a first threshold voltage using a first threshold detection and control circuit, and turning off at least one of the first FET or the second FET using the first threshold detection and control circuit when the voltage of the first terminal is greater than the first threshold voltage;

comparing the voltage of the input terminal to a second threshold voltage using a second threshold detection and control circuit, and turning off at least one of the first FET or the second FET using the second threshold detection and control circuit when the voltage of the first terminal is less than the second threshold voltage; and

turning on the first and second FETs using a gate bias circuit when neither the first threshold detection and control circuit nor the second threshold detection and control circuit is active to turn off the first or second FETs.