WIDE BAND GAP SEMICONDUCTOR DEVICE

• US 20140145209A1
• Filed: 11/15/2013
• Published: 05/29/2014
• Est. Priority Date: 11/29/2012
• Status: Active Grant

• Current Assignee: Fuji Electric Company Limited (Fuji Electric Systems Company Limited)
• Original Assignee: Fuji Electric Company Limited (Fuji Electric Systems Company Limited)
• Inventors: KUMAGAI, Naoki
• Granted Patent: US 9,349,855 B2
• Time in Patent Office: Days
• US Class Current: 257/77
• CPC Class Codes: H01L 29/0696 of cellular field-effect devices, e.g. multicellular DMOS transistors or IGBTs
• CPC Class Codes: H01L 29/0865 Disposition
• CPC Class Codes: H01L 29/0878 Impurity concentration or distribution
• CPC Class Codes: H01L 29/1095 Body region, i.e. base region, of DMOS transistors or IGBTs cell layout H01L29/0696
• CPC Class Codes: H01L 29/1608 Silicon carbide
• CPC Class Codes: H01L 29/41766 with at least part of the source or drain electrode having contact below the semiconductor surface, e.g. the source or drain electrode formed at least partially in a groove or with inclusions of conductor inside the semiconductor H01L29/41733 - H01L29/41758 take precedence
• CPC Class Codes: H01L 29/4236 within a trench, e.g. trench gate electrode, groove gate electrode
• CPC Class Codes: H01L 29/42368 the thickness being non-uniform
• CPC Class Codes: H01L 29/7813 with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236

Abstract

A semiconductor device comprises an n+ type SiC semiconductor substrate, an n type low concentration drift layer of an SiC semiconductor on the substrate, p type channel regions selectively arranged in the drift layer with a specified distance between the channel regions, an n type source region selectively arranged in the channel region, a source electrode in common contact with the source region and the channel region, and a gate electrode disposed over the drift layer between two channel regions, and over a part of the channel region positioned between the drift layer and the source region intercalating a gate oxide film therebetween. The drift layer has a low concentration of at most 70% of the concentration that is required to exhibit a specified withstand voltage at a minimum ON resistance.

Claims

1. A wide band gap semiconductor device comprising:

a wide band gap semiconductor substrate of a first conductivity type with a high impurity concentration;

a drift layer of the first conductivity type with a low impurity concentration composed of a wide band gap semiconductor material on the substrate;

a plurality of channel regions of a second conductivity type selectively arranged in a surface region of the drift layer with a specified distance between the channel regions;

a source region of the first conductivity type selectively arranged in a surface region of the plurality of channel regions of the second conductivity type;

a source electrode in common contact with a surface of the source region and a surface of the plurality of channel regions; and

a gate electrode disposed over a surface of the surface region of the drift layer positioned between the plurality of channel regions and over surfaces of the plurality of channel regions each positioned between the surface region of the drift layer and the source region, intercalating a gate oxide film beneath the gate electrode;

wherein the drift layer of the first conductivity type with a low impurity concentration composed of a wide band gap semiconductor material has a low impurity concentration not higher than 70% of an impurity concentration that is required to exhibit a specified withstand voltage at a minimum ON resistance.

2. The wide band gap semiconductor device according to claim 1, wherein the drift layer of the first conductivity type with a low impurity concentration composed of a wide band gap semiconductor material has a low impurity concentration not higher than 50% of the impurity concentration that is required to exhibit a specified withstand voltage at a minimum ON resistance.

3. The wide band gap semiconductor device according to claim 1, wherein the drift layer of the first conductivity type with a low impurity concentration composed of a wide band gap semiconductor material has a low impurity concentration of at least 25% of the impurity concentration that is required to exhibit a specified withstand voltage at a minimum ON resistance.

4. The wide band gap semiconductor device according to claim 1, wherein an impurity concentration in the surface region of the drift layer positioned between the plurality of channel regions is higher than an impurity concentration in another portion of the drift layer.

5. The wide band gap semiconductor device according to claim 1, wherein a thickness of a part of the gate oxide film that is in contact with the surface region of the drift layer positioned between the plurality of channel regions is thicker than a thickness of a part of the gate oxide film that is in contact with a surface of the plurality of channel regions positioned between the surface region of the drift layer and the source region.

6. The wide band gap semiconductor device according to claim 1, wherein the wide band gap semiconductor material is selected from the group consisting of silicon carbide (SiC) semiconductor, gallium nitride (GaN) semiconductor, and diamond.

11. The wide band gap semiconductor device according to claim 2, wherein an impurity concentration in the surface region of the drift layer positioned between the channel regions is higher than an impurity concentration in another portion of the drift layer.

12. The wide band gap semiconductor device according to claim 3, wherein an impurity concentration in the surface region of the drift layer positioned between the channel regions is higher than an impurity concentration in another portion of the drift layer.

7. A wide band gap semiconductor device comprising:

a wide band gap semiconductor substrate of a first conductivity type with a high impurity concentration;

a drift layer of the first conductivity type with a low impurity concentration composed of a wide band gap semiconductor material on the substrate;

a channel region of a second conductivity type selectively formed in a surface region of the drift layer;

a source region of the first conductivity type selectively arranged in a surface region of the channel region of the second conductivity type;

a source electrode in common contact with a surface of the source region and a surface of the channel region;

a plurality of gate trenches formed from a surface of the source region of the first conductivity type through the channel region reaching the drift layer; and

a gate electrode embedded in each of the gate trenches interposing a gate oxide film on an inner surface of the gate trench;

wherein an impurity concentration of the drift layer of the first conductivity type with a low impurity concentration composed of a wide band gap semiconductor material is in a range from 33% to 60% of an impurity concentration that is required to exhibit a specified withstand voltage at a minimum ON resistance.

8. The wide band gap semiconductor device according to claim 7, wherein the gate oxide film is thicker on a bottom of the trench than on a side wall of the trench.

10. The wide band gap semiconductor device according to claim 7, wherein the wide band gap semiconductor material is selected from the group consisting of silicon carbide (SiC) semiconductor, gallium nitride (GaN) semiconductor, and diamond.

9. A wide band gap semiconductor device comprising:

a wide band gap semiconductor substrate of a first conductivity type with a high impurity concentration;

a drift layer of the first conductivity type with a low impurity concentration composed of a wide band gap semiconductor material on the substrate;

a channel region of a second conductivity type selectively formed in a surface region of the drift layer;

a source region of the first conductivity type selectively arranged in a surface region of the channel region of the second conductivity type;

a source electrode in common contact with a surface of the source region and a surface of the channel region;

a plurality of gate trenches and a plurality of source trenches, each of the gate trenches and the source trenches being formed from a surface of the source region of the first conductivity type through the channel region reaching the drift layer and being arranged alternately;

a gate electrode embedded in each of the gate trenches interposing a gate oxide film on an inner surface of the gate trench; and

a base region of the second conductivity type with a high impurity concentration disposed at a bottom of each of the source trenches;

wherein the source electrode that is in common contact with the base region and the source region both exposing to a side wall of the source trench is embedded in the source trench, and

wherein an impurity concentration of the drift layer of the first conductivity type with a low impurity concentration composed of a wide band gap semiconductor material is in a range from 33% to 60% of an impurity concentration that is required to exhibit a specified withstand voltage at a minimum ON resistance.

13. The wide band gap semiconductor device according to claim 9, wherein the wide band gap semiconductor material is selected from the group consisting of silicon carbide (SiC) semiconductor, gallium nitride (GaN) semiconductor, and diamond.

14. A device, comprising:

a wide-band gap semiconductor substrate of a first conductivity type;

a drift layer of the first conductivity type on the wide-band gap semiconductor substrate;

at least one channel region of a second conductivity type in the drift layer;

a source region of the first conductivity type in the at least one channel region; and

a source electrode and a gate electrode over the drift layer;

wherein the drift layer has an impurity concentration not higher than 70% of 1.3×

10¹⁶ cm<sup>−

3</sup>.

15. The device of claim 14, wherein the impurity concentration is not higher than 50% of 1.3×

10¹⁶ cm<sup>−

3</sup>.

16. The device of claim 14, wherein the impurity concentration is between 25% and 70% of 1.3×

10¹⁶ cm<sup>−

3</sup>.

17. The device of claim 14, wherein the impurity concentration is between 25% and 50% of 1.3×

10¹⁶ cm<sup>−

3</sup>.