METHOD FOR CONTROLLING SIGNAL VALUE ON GATE LINE, GATE DRIVING CIRCUIT AND DISPLAY DEVICE

• US 20140146025A1
• Filed: 11/27/2013
• Published: 05/29/2014
• Est. Priority Date: 11/29/2012
• Status: Active Grant

• Current Assignee: Beijing BOE Optoelectronics Technology Co Ltd. (BOE Technology Group Co., Ltd.)
• Original Assignee: Beijing BOE Optoelectronics Technology Co Ltd. (BOE Technology Group Co., Ltd.)
• Inventors: SHI, Lingyun, ZHENG, Yi, LIU, Rui
• Granted Patent: US 9,530,365 B2
• Time in Patent Office: Days
• US Class Current: 345/204
• CPC Class Codes: G02F 1/1345 Conductors connecting electrodes to cell terminals
• CPC Class Codes: G02F 1/136286 Wiring, e.g. gate line, drain line
• CPC Class Codes: G09G 2300/0408 Integration of the drivers onto the display substrate
• CPC Class Codes: G09G 2300/0426 Layout of electrodes and connections
• CPC Class Codes: G09G 2310/0278 Details of driving circuits arranged to drive both scan and data electrodes
• CPC Class Codes: G09G 2320/0223 Compensation for problems related to R-C delay and attenuation in electrodes of matrix panels, e.g. in gate electrodes or on-substrate video signal electrodes
• CPC Class Codes: G09G 3/3648 using an active matrix G09G3/367 - G09G3/3696 take precedence
• CPC Class Codes: G09G 3/3677 suitable for active matrices only

Abstract

The disclosure relates to a method for controlling signal values on gate lines, a gate driving circuit and a display device. The method comprises: for each of gate lines in the valid display area, in a first frame in any two adjacent frames of image, connecting a gate connecting line in a first layer to a gate line by a first strobe unit and applying a first signal value to the gate line; in a second frame, connecting a gate connecting line in a second layer to the gate line by a second strobe unit and applying a second signal value to the gate line. It may address the issue of H-line Mura due to different impedances of wires in the gate layer and the S/D layer.

Claims

1. A method for controlling signal values on gate lines in a valid display area, wherein the method comprises:

for each of gate lines in the valid display area, in a first frame in any two adjacent frames of image, connecting a gate connecting line in a first layer to the gate line by a first strobe unit and applying a first signal value to the gate line via the gate connecting line in the first layer;

in a second frame in the two adjacent frames of image, connecting a gate connecting line in a second layer to the gate line by a second strobe unit and applying a second signal value to the gate line via the gate connecting line in the second layer;

wherein the gate connecting line in the first layer and the gate connecting line in the second layer are located in different layers of a Fan-out area on a display substrate, for connecting a signal source and the gate line.

2. The method of claim 1, wherein the connecting the gate connecting line in the first layer to a gate line by a first strobe unit and applying a first signal value to the gate line via the gate connecting line in the first layer comprises:

controlling the first strobe unit by a first control signal to connect the gate connecting line in the first layer to the gate line;

controlling the second strobe unit by a second control signal to disconnect the gate connecting line in the second layer from the gate line;

wherein the connecting the gate connecting line in the second layer to the gate line by a second strobe unit and applying a second signal value to the gate line via the gate connecting line in the second layer comprises;

controlling the first strobe unit by the first control signal to disconnect the gate connecting line in the first layer from the gate line;

controlling the second strobe unit by the second control signal to connect the gate connecting line in the second layer to the gate line.

3. The method of claim 2, wherein the first control signal and the second control signal are clock pulse signals whose high-low levels are compensated, and the high-low level of each of the clock pulse signals is converted between two adjacent frames of image.

4. The method of claim 1, wherein before applying the first signal value or the second signal value to the gate line via the gate connecting line in the first layer or the gate connecting line in the second layer, the method further comprises:

for the respective gate connecting lines, applying initial signals with a same initial value to the respective gate connecting lines by signal sources to which the corresponding gate connecting lines are connected.

5. The method of claim 1, wherein before applying the first signal value or the second signal value to the gate line via the gate connecting line in the first layer or the gate connecting line in the second layer, the method further comprises:

applying initial signals with different initial values to the respective gate connecting lines by the signal sources to which the corresponding gate connecting lines are connected, based on impedance of the respective gate connecting lines.

6. The method of claim 1, further comprising:

dividing the gate lines in the valid display area into a plurality of gate line groups each comprising one or more adjacent gate lines;

wherein, in one frame of image, the signal values applied to the gate lines in a same group are transmitted by the gate connecting lines in a same layer, and the signal values applied to the gate lines in two adjacent groups are transmitted by the gate connecting lines in different layers.

7. A gate driving circuit comprising an integrated circuit driving module and a driving control module;

wherein the driving control module comprises one or more first strobe units, one or more second strobe units, one or more gate connecting lines in a first layer, one or more gate connecting lines in a second layer, one or more first gate lines and one or more second gate lines;

wherein the first strobe unit comprises a P-type Metal Oxide Semiconductor (PMOS) transistor and an N-type Metal Oxide Semiconductor (NMOS) transistor, a same signal is applied to gates of the PMOS transistor and the NMOS transistor, and a gate connecting line in the first layer is connected to a drain of the NMOS transistor and a source of the PMOS transistor in the first strobe unit;

the second strobe unit comprises a PMOS transistor and a NMOS transistor, wherein a same signal is applied to gates of the PMOS transistor and the NMOS transistor, a gate connecting line in the second layer is connected to a drain of the NMOS transistor and a source of the PMOS transistor in the second strobe unit;

the integrated circuit driving module generates gate driving signals and transmits the gate driving signals to the driving control module;

wherein the gate connecting line in the first layer and the gate connecting line in the second layer are located in different layers of a Fan-out area on a display substrate, for connecting the gate driving signal and the gate line;

the first gate line and the second gate line are two adjacent gate lines located in each gate line group in a valid display area.

8. The gate driving circuit of claim 7, wherein the first gate line is connected to the source of the NMOS transistor in the first strobe unit and the source of the NMOS transistor in the second strobe unit, respectively, and the second gate line is connected to the drain of the PMOS transistor in the first strobe unit and the drain of the PMOS transistor in the second strobe unit, respectively;

for a first frame in any two adjacent frames of image, the driving control module connects the gate connecting line in the first layer to the first gate line by applying a first control signal to gates of the PMOS transistor and NMOS transistor in the first strobe unit, and applies a first signal value to the first gate line via the gate connecting line in the first layer, and connects the gate connecting line in the second layer to the second gate line by applying a second control signal to gates of the PMOS transistor and NMOS transistor in the second strobe unit, and applies a second signal value to the second gate line via the gate connecting line in the second layer; and

for a second frame in the two adjacent frames of image, the driving control module connects the gate connecting line in the first layer to the second gate line by applying the second control signal to the gates of the PMOS transistor and NMOS transistor in the first strobe unit, and applies the first signal value to the second gate line via the gate connecting line in the first layer, and connects the gate connecting line in the second layer to the first gate line by applying the first control signal to the gates of the PMOS transistor and NMOS transistor in the second strobe unit, and applies the second signal value to the first gate line via the gate connecting line in the second layer.

9. The gate driving circuit of claim 7, wherein the first gate line is connected to the source of the NMOS transistor in the first strobe unit and the drain of the PMOS transistor in the second strobe unit, respectively, and the second gate line is connected to the drain of the PMOS transistor in the first strobe unit and the source of the NMOS transistor in the second strobe unit, respectively;

for a first frame in any two adjacent frames of image, the driving control module further connects the gate connecting line in the first layer to the first gate line by applying a first control signal to gates of the PMOS transistor and the NMOS transistor in the first strobe unit, and applies a first signal value to the first gate line via the gate connecting line in the first layer, and connects the gate connecting line in the second layer to the second gate line by applying a first control signal to gates of the PMOS transistor and NMOS transistor in the second strobe unit, and applies a second signal value to the second gate line via the gate connecting line in the second layer; and

for a second frame in the two adjacent frames of image, the driving control module connects the gate connecting line in the first layer to the second gate line by applying the second control signal to the gates of the PMOS transistor and NMOS transistor in the first strobe unit, and applies the first signal value to the second gate line via the gate connecting line in the first layer, and connects the gate connecting line in the second layer to the first gate line by applying the second control signal to the gates of the PMOS transistor and NMOS transistor in the second strobe unit, and applies the second signal value to the first gate line via the gate connecting line in the second layer.

10. A display apparatus comprising a gate driving circuit, wherein the gate driving circuit comprises an integrated circuit driving module and a driving control module;

wherein the driving control module comprises one or more first strobe units, one or more second strobe units, one or more gate connecting lines in a first layer, one or more gate connecting lines in a second layer, one or more first gate lines and one or more second gate lines;

wherein the first strobe unit comprises a P-type Metal Oxide Semiconductor (PMOS) transistor and an N-type Metal Oxide Semiconductor (NMOS) transistor, a same signal is applied to gates of the PMOS transistor and the NMOS transistor, and a gate connecting line in the first layer is connected to a drain of the NMOS transistor and a source of the PMOS transistor in the first strobe unit;

the second strobe unit comprises a PMOS transistor and a NMOS transistor, wherein a same signal is applied to gates of the PMOS transistor and the NMOS transistor, a gate connecting line in the second layer is connected to a drain of the NMOS transistor and a source of the PMOS transistor in the second strobe unit;

the integrated circuit driving module generates gate driving signals and transmits the gate driving signals to the driving control module;

wherein the gate connecting line in the first layer and the gate connecting line in the second layer are located in different layers of a Fan-out area on a display substrate, for connecting the gate driving signal and the gate line;

the first gate line and the second gate line are two adjacent gate lines located in each gate line group in a valid display area.

11. The display apparatus of claim 10, wherein the first gate line is connected to the source of the NMOS transistor in the first strobe unit and the source of the NMOS transistor in the second strobe unit, respectively, and the second gate line is connected to the drain of the PMOS transistor in the first strobe unit and the drain of the PMOS transistor in the second strobe unit, respectively;

for a first frame in any two adjacent frames of image, the driving control module connects the gate connecting line in the first layer to the first gate line by applying a first control signal to gates of the PMOS transistor and NMOS transistor in the first strobe unit, and applies a first signal value to the first gate line via the gate connecting line in the first layer, and connects the gate connecting line in the second layer to the second gate line by applying a second control signal to gates of the PMOS transistor and NMOS transistor in the second strobe unit, and applies a second signal value to the second gate line via the gate connecting line in the second layer; and

for a second frame in the two adjacent frames of image, the driving control module connects the gate connecting line in the first layer to the second gate line by applying the second control signal to the gates of the PMOS transistor and NMOS transistor in the first strobe unit, and applies the first signal value to the second gate line via the gate connecting line in the first layer, and connects the gate connecting line in the second layer to the first gate line by applying the first control signal to the gates of the PMOS transistor and NMOS transistor in the second strobe unit, and applies the second signal value to the first gate line via the gate connecting line in the second layer.

12. The display apparatus of claim 10, wherein the first gate line is connected to the source of the NMOS transistor in the first strobe unit and the drain of the PMOS transistor in the second strobe unit, respectively, and the second gate line is connected to the drain of the PMOS transistor in the first strobe unit and the source of the NMOS transistor in the second strobe unit, respectively;

for a first frame in any two adjacent frames of image, the driving control module further connects the gate connecting line in the first layer to the first gate line by applying a first control signal to gates of the PMOS transistor and the NMOS transistor in the first strobe unit, and applies a first signal value to the first gate line via the gate connecting line in the first layer, and connects the gate connecting line in the second layer to the second gate line by applying a first control signal to gates of the PMOS transistor and NMOS transistor in the second strobe unit, and applies a second signal value to the second gate line via the gate connecting line in the second layer; and

for a second frame in the two adjacent frames of image, the driving control module connects the gate connecting line in the first layer to the second gate line by applying the second control signal to the gates of the PMOS transistor and NMOS transistor in the first strobe unit, and applies the first signal value to the second gate line via the gate connecting line in the first layer, and connects the gate connecting line in the second layer to the first gate line by applying the second control signal to the gates of the PMOS transistor and NMOS transistor in the second strobe unit, and applies the second signal value to the first gate line via the gate connecting line in the second layer.