SOLID-STATE IMAGING DEVICE AND DRIVING METHOD OF SOLID-STATE IMAGING DEVICE

• US 20140146211A1
• Filed: 01/29/2014
• Published: 05/29/2014
• Est. Priority Date: 08/08/2011
• Status: Active Grant

• Current Assignee: Panasonic Intellectual Property Management Co., Ltd. (Panasonic Holdings Corporation)
• Original Assignee: Panasonic Corporation (Panasonic Holdings Corporation)
• Inventors: MORI, Mitsuyoshi, SAKATA, Yusuke, HIROSE, Yutaka, MIYAGAWA, Ryohei, DOI, Hiroyuki, TSUTSUI, Masafumi
• Granted Patent: US 9,197,830 B2
• Time in Patent Office: Days
• US Class Current: 348/308
• CPC Class Codes: H04N 25/616 involving a correlated sampling function, e.g. correlated double sampling [CDS] or triple sampling
• CPC Class Codes: H04N 25/65 applied to reset noise, e.g. KTC noise related to CMOS structures by techniques other than CDS
• CPC Class Codes: H04N 25/76 Addressed sensors, e.g. MOS or CMOS sensors
• CPC Class Codes: H04N 25/767 Horizontal readout lines, multiplexers or registers
• CPC Class Codes: H04N 25/77 Pixel circuitry, e.g. memories, A/D converters, pixel amplifiers, shared circuits or shared components
• CPC Class Codes: H04N 25/79 Arrangements of circuitry being divided between different or multiple substrates, chips or circuit boards, e.g. stacked image sensors

Abstract

A solid-state imaging device includes: an epilayer; pixel electrodes; a photoelectric converting film formed above the pixel electrodes and converting incident light into electric signals; a transparent electrode formed on the photoelectric converting film;

charge accumulating regions of an n-type each (i) formed in the epilayer to correspond to one of the pixel electrodes, (ii) electrically connected to the one corresponding pixel electrode, and (iii) accumulating signal charges generated by the photoelectric converting film through the photo-electrically conversion; charge barrier regions of a p-type each formed in the epilayer to contact a bottom of a corresponding one of the charge accumulating regions; and charge draining regions of an n-type each formed in the epilayer to contact a bottom of a corresponding one of the charge barrier regions.

Claims

1. A solid-state imaging device comprising:

a substrate;

a first electrode formed above the substrate;

a photoelectric converting film formed above the first electrode and converting light into signal charges;

a second electrode formed on the photoelectric converting film;

a charge accumulating unit formed on the substrate, electrically connected to the first electrode, and configured to accumulate charges flowing from the first electrode;

a reset transistor having a drain electrically connected to the charge accumulating unit;

a signal readout circuit electrically connected to the charge accumulating unit, and generating a readout signal which is an electric signal and whose level is based on an amount of the charges accumulated in the charge accumulating unit; and

a control circuit (i) applying a turn-on voltage to a gate of the reset transistor while applying a first voltage to a source of the reset transistor, and (ii) varying a voltage being applied to the source from the first voltage to a second voltage while applying the turn-on voltage to the gate, the turn-on voltage turning on the gate of the reset transistor, the first voltage repelling the charges accumulated in the charge accumulating unit, and the second voltage attracting the charges accumulated in the charge accumulating unit.

2. The solid-state imaging device according to claim 1,

wherein, while the gate of the reset transistor is on, the control circuit gradually varies the voltage being applied to the source from the first voltage to the second voltage, so that a time period for the gradual variation takes longer than or equal to a time period required for a pulse to the gate to either rise or fall.

3. The solid-state imaging device according to claim 1, further comprising

a comparator comparing the readout signal with a first reference level,

wherein if the comparator determines that the level of the readout signal is lower than or equal to the first reference level, the control circuit stops the variation in the voltage being applied to the source and applies the turn-on voltage to the gate while keeping the voltage being applied to the source fixed to the second voltage.

4. The solid-state imaging device according to claim 3,

wherein the comparator further compares the readout signal with a second reference level which is higher than the first reference level, and

if the comparator determines that the level of the readout signal is higher than the second reference level, the control circuit (i) applies the turn-on voltage to the gate while applying the first voltage to the source, (ii) varies the voltage being applied to the source from the first voltage to the second voltage while applying the turn-on voltage to the gate, and (iii) continuously applies the turn-on voltage to the gate after the variation.

5. The solid-state imaging device according to claim 4,

wherein the first electrode is formed electrically separated into sub first electrodes,

the sub first electrodes each corresponds to one of (i) charge accumulating units including the charge accumulating unit, (ii) reset transistors including the reset transistor, (iii) signal readout circuits including the signal readout circuit, (iv) control circuits including the control circuit, and (v) comparators including the comparator, and

one of the control circuits causes another one of the control circuits to continuously apply the turn-on voltage to a gate of one of the reset transistors corresponding to the other control circuit, if one of the comparators corresponding to the one control circuit determines that a level of a readout signal for the one comparator is higher than the second reference level.

6. The solid-state imaging device according to claim 1,

wherein the charge accumulating unit is configured to accumulate holes as the charges, and

the control circuit (i) turns on the gate of the reset transistor while applying a positive voltage as the first voltage to the source of the reset transistor, and (ii) decreases a voltage being applied to the source of the reset transistor from the first voltage to the second voltage while leaving the gate of the reset transistor on, the second voltage being lower than the first voltage.

7. The solid-state imaging device according to claim 1,

wherein the charge accumulating unit is configured to accumulate electrons as the charges, and

the control circuit (i) turns on the gate of the reset transistor while applying a negative voltage as the first voltage to the source of the reset transistor, and (ii) increases a voltage being applied to the source of the reset transistor from the first voltage to the second voltage while leaving the gate of the reset transistor on, the second voltage being higher than the first voltage.

8. A method for driving a solid-state imaging device which includes:

a substrate;

a first electrode formed above the substrate;

a photoelectric converting film formed above the first electrode and converting light into signal charges;

a second electrode formed on the photoelectric converting film;

a charge accumulating unit formed on the substrate, electrically connected to the first electrode, and configured to accumulate charges flowing from the first electrode;

a reset transistor has a gate electrically connected to the charge accumulating unit;

a signal readout circuit electrically connected to the charge accumulating unit, and generating a readout signal whose level is based on an amount of charges accumulated in the charge accumulating unit; and

a control circuit which independently supplies a voltage to each of a source and a gate of the reset transistor,

the method comprising;

applying by the control circuit a turn-on voltage to the gate of the reset transistor to turn the gate on while applying by the control circuit a first voltage to the source of the reset transistor, the first voltage repelling the charges accumulated in the charge accumulating unit; and

varying by the control unit a voltage being applied to the source from the first voltage to the second voltage while applying by the control unit the turn-on voltage to the gate, the second voltage attracting the charges accumulated in the charge accumulating unit.

9. A solid-state imaging device comprising:

a semiconductor substrate; and

a plurality of unit pixels disposed on the semiconductor substrate, wherein each of the plurality of unit pixels includes;

a first electrode;

a photoelectric converting film disposed on the first electrode and converting light into an electric signal;

a second electrode disposed on the photoelectric converting film;

a charge accumulating region of first conductivity, the charge accumulating region being electrically connected to the first electrode, and the charge accumulating region accumulating charges generated by the photoelectric converting film through photo-electrical conversion;

a charge barrier region of second conductivity disposed in contact with a bottom of the charge accumulating region, the second conductivity being electrically opposite the first conductivity; and

a charge draining region of the first conductivity disposed in contact with a bottom of the charge barrier region.

10. The solid-state imaging device according to claim 9,

wherein the charge barrier region is lower in impurity concentration than the charge draining region.

11. The solid-state imaging device according to claim 9, further comprising

a metal-oxide-semiconductor (MOS) transistor initializing a potential of the charge accumulating region,

wherein the charge accumulating region also works as one of a drain region and a source region of the MOS transistor,

an other one of the drain region and the source region of the MOS transistor is of the first conductivity, and

from a top surface of the semiconductor substrate, the charge accumulating region is formed deeper than the other one of the drain region and the source region is.

12. The solid-state imaging device according to claim 9,

wherein the charge draining region contacts the semiconductor substrate of the second conductivity.

13. The solid-state imaging device according to claim 9,

wherein a potential of the charge draining region varies.