MEMORY SYSTEM HAVING VARIABLE OPERATING VOLTAGE AND RELATED METHOD OF OPERATION
First Claim
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1. A magneto-resistive random access memory (MRAM), comprising:
- an MRAM cell array having an MRAM cell; and
a control and voltage generation unit configured to generate a back bias voltage for the MRAM cell,wherein the control and voltage generation unit comprises;
a command decoder configured to generate a decoding signal in response to a command output from a memory controller; and
a voltage controller and generator configured to generate the back bias voltage with a magnitude based on the decoding signal and a reset signal output from the memory controller.
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Abstract
A magneto-resistive random access memory (MRAM) comprising an MRAM cell array having an MRAM cell, and a control and voltage generation unit configured to generate a back bias voltage for the MRAM cell. The control and voltage generation unit comprising a command decoder configured to generate a decoding signal in response to a command output from a memory controller, and a voltage controller and generator configured to generate the back bias voltage with a magnitude based on the decoding signal and a reset signal output from the memory controller.
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Citations
15 Claims
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1. A magneto-resistive random access memory (MRAM), comprising:
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an MRAM cell array having an MRAM cell; and a control and voltage generation unit configured to generate a back bias voltage for the MRAM cell, wherein the control and voltage generation unit comprises; a command decoder configured to generate a decoding signal in response to a command output from a memory controller; and a voltage controller and generator configured to generate the back bias voltage with a magnitude based on the decoding signal and a reset signal output from the memory controller. - View Dependent Claims (2, 3)
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4. A memory system, comprising:
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a memory controller comprising a control unit configured to generate a command and a voltage selection signal; and a magneto-resistive random access memory (MRAM) comprising a MRAM cell array having an MRAM cell, and a control and voltage generation unit configured to generate an operating voltage for the MRAM cell, wherein the control and voltage generation unit comprises; a command decoder configured to generate a decoding signal in response to the command; and a voltage controller and generator configured to generate the operating voltage with a magnitude determined by the decoding signal and the voltage selection signal. - View Dependent Claims (5, 6, 7, 8, 9, 10, 11)
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12. A memory system, comprising:
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a memory controller comprising a control unit configured to generate a command and a reset signal; and a magneto-resistive random access memory (MRAM) comprising an MRAM cell array having an MRAM cell, and a control and voltage generation unit configured to generate a back bias voltage for the MRAM cell, wherein the control and voltage generation unit comprises; a command decoder configured to generate a decoding signal in response to the command; and a voltage controller and generator configured to generate the back bias voltage with a magnitude based on the decoding signal and the reset signal. - View Dependent Claims (13, 14, 15)
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Specification