SERIAL DIGITAL INTERFACE BETWEEN AN RF TRANSCEIVER AND A BASEBAND CHIP

• US 20140146861A1
• Filed: 11/20/2013
• Published: 05/29/2014
• Est. Priority Date: 11/27/2012
• Status: Active Grant

• Current Assignee: Nanjing Aviacomm Semiconductor Company Limited
• Original Assignee: Aviacomm Inc.
• Inventors: Li, Tao, Wang, Hans, Zhang, Binglei, Mo, Shih Hsiung
• Granted Patent: US 9,059,779 B2
• Time in Patent Office: Days
• US Class Current: 375/219
• CPC Class Codes: H03M 9/00 Parallel/series conversion or vice versa digital stores in which the information is moved stepwise per se G11C19/00
• CPC Class Codes: H04B 1/40 Circuits
• CPC Class Codes: H04B 10/40 Transceivers
• CPC Class Codes: H04L 65/1101 Session protocols
• CPC Class Codes: H04L 7/0041 Delay of data signal
• CPC Class Codes: H04L 7/041 using special codes as synchronising signal
• CPC Class Codes: H04M 1/738 Interface circuits for coupling substations to external telephone lines H04M1/78 takes precedence
• CPC Class Codes: H04Q 2213/13034 A/D conversion, code compression/expansion
• CPC Class Codes: H04Q 2213/13248 Multimedia

Abstract

One embodiment of the present invention provides a device for interfacing between a baseband controller and an RF integrated circuit (IC) chip having a modulator and a demodulator. The device includes an analog-to-digital converter (ADC) coupled to the demodulator located on the RF IC chip. The ADC is configured to receive demodulated analog signals from the demodulator. The device further includes a serializer configured to generate a serial data frame based on the ADC'"'"'s output, a first serial data port configured to send the serial data frame to the baseband controller, and a control module coupled to the baseband controller.

Claims

1. A device for interfacing between a baseband controller and an RF integrated circuit (IC) chip having a modulator and a demodulator, comprising:

an analog-to-digital converter (ADC) coupled to the demodulator located on the RF IC chip, wherein the ADC is configured to receive demodulated analog signals from the demodulator;

a serializer configured to generate a serial data frame based on the ADC'"'"'s output;

a first serial data port configured to send the serial data frame to the baseband controller; and

a control module coupled to the baseband controller.

2. The device of claim 1, further comprising:

a deserializer coupled to the baseband controller, wherein the deserializer is configured to receive serial data from the baseband controller, and wherein the deserializer is configured to convert the serial data received from the baseband controller to parallel data;

a DAC configured to convert the parallel data to analog signals; and

an analog output configured to send the converted analog signals to the modulator.

3. The device of claim 1, further comprising a signal converter configured to convert between single-ended digital signals and differential digital signals.

4. The device of claim 3, wherein the differential digital signals are low-voltage differential signaling (LVDS) signals.

5. The device of claim 1, further comprising a clock module configured to provide clock signals to at least the ADC and the serializer.

6. The device of claim 1, wherein the control module includes at least a configuration register for controlling at least the ADC and the serializer, and a status register for indicating status of the serial data frame.

7. The device of claim 6, wherein the ADC and the serializer are configured to be powered down by the baseband controller setting a particular bit in the configuration register.

8. The device of claim 1, wherein the control module is coupled to the baseband controller via a serial peripheral interface.

9. A wireless transceiver, comprising:

an RF integrated circuit (IC) chip that comprises a modulator and a demodulator;

a baseband controller; and

an interfacing device configured to couple the RF IC chip with the baseband controller, wherein the interfacing device comprises;

an analog-to-digital converter (ADC) coupled to the demodulator, wherein the ADC is configured to receive demodulated analog signals from the demodulator;

a serializer configured to generate a serial data frame based on the ADC'"'"'s output;

a first serial data port coupled to the baseband controller, wherein the first serial port is configured to send the serial data frame to the baseband controller; and

a control module coupled to the baseband controller.

10. The transceiver of claim 9, wherein the interfacing device further comprises:

a deserializer coupled to the baseband controller, wherein the deserializer is configured to receive serial data from the baseband controller, and wherein the deserializer is configured to convert the serial data received from the baseband controller to parallel data;

a DAC configured to convert the parallel data to analog signals; and

an analog output coupled to the modulator, wherein the analog output is configured to send the converted analog signals to the modulator.

11. The transceiver of claim 9, wherein the interfacing device further comprises a signal converter configured to convert between single-ended digital signals and differential digital signals.

12. The transceiver of claim 11, wherein the differential digital signals are low-voltage differential signaling (LVDS) signals.

13. The transceiver of claim 9, wherein the interfacing device further comprises a clock module configured to provide clock signals to at least the ADC and the serializer.

14. The transceiver of claim 9, wherein the control module includes at least a configuration register for controlling at least the ADC and the serializer, and a status register for indicating status of the serial data frame.

15. The transceiver of claim 14, wherein the ADC and the serializer are configured to be powered down by the baseband controller setting a particular bit in the configuration register.

16. The transceiver of claim 9, wherein the control module is coupled to the baseband controller via a serial peripheral interface.