METHOD AND SYSTEM FOR PERFORMING DATA TRANSFER WITH A FLASH STORAGE MEDIUM

• US 20140149637A1
• Filed: 11/23/2012
• Published: 05/29/2014
• Est. Priority Date: 11/23/2012
• Status: Active Grant

• Current Assignee: Hong Kong Applied Science And Technology Research Institute Co., Ltd.
• Original Assignee: Hong Kong Applied Science And Technology Research Institute Co., Ltd.
• Inventors: GU, Weiqing, WANG, Xiaoji, TANG, Xianzhi, SUN, Conghao, CHEN, Fangyao
• Granted Patent: US 9,098,491 B2
• Time in Patent Office: Days
• US Class Current: 711/103
• CPC Class Codes: G06F 12/0868 Data transfer between cache memory and other subsystems, e.g. storage devices or host systems
• CPC Class Codes: G06F 13/00 Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units interface circuits for specific input/output devices G06F3/00 ; multiprogram control therefor G06F9/46; multiprocessor systems G06F15/16
• CPC Class Codes: G06F 13/12 using hardware independent of the central processor, e.g. channel or peripheral processor
• CPC Class Codes: G06F 13/1673 using buffers
• CPC Class Codes: G06F 13/28 using burst mode transfer, e.g. direct memory access DMA, cycle steal G06F13/32 takes precedence
• CPC Class Codes: G06F 3/0601 Interfaces specially adapted for storage systems
• CPC Class Codes: G06F 3/0602 specifically adapted to achieve a particular effect
• CPC Class Codes: G06F 3/0604 Improving or facilitating administration, e.g. storage management
• CPC Class Codes: G06F 3/0607 by facilitating the process of upgrading existing storage systems, e.g. for improving compatibility between host and storage device
• CPC Class Codes: G06F 3/0628 making use of a particular technique
• CPC Class Codes: G06F 3/0646 Horizontal data movement in storage systems, i.e. moving data in between storage devices or systems
• CPC Class Codes: G06F 3/0655 Vertical data movement, i.e. input-output transfer; data movement between one or more hosts and one or more storage devices
• CPC Class Codes: G06F 3/0656 Data buffering arrangements

Abstract

This invention discloses a method for data transfer between a host memory and a flash memory module through direct memory access (DMA), and a related data-transfer subsystem. In one embodiment, the subsystem comprises a DMA controller, a flash-memory controller, a data buffer for buffering data transferred between the DMA controller and the flash-memory controller, and a status-register group for storing a current status of the data buffer. The DMA controller and the flash-memory controller are configured such that both of them are allowed to update the current status and to detect a change of the current status during the data transfer, so that a substantial part of the data transfer'"'"'s process is executed through direct interaction between the DMA controller and the flash-memory controller without involving a central processing unit. The subsystem may further comprise a command storing unit for storing command packages for execution by the flash-memory controller.

Claims

1. A data-transfer subsystem configured to enable data transfer through direct memory access (DMA) between a host memory and any of one or more flash memory modules supportable by the subsystem, the subsystem comprising:

a DMA controller for at least transferring data to and from the host memory;

a flash-memory controller for at least transferring data to and from any of the one or more flash memory modules;

a data buffer coupled to the DMA controller and the flash-memory controller, for buffering data transferred between the DMA controller and the flash-memory controller; and

a status-register group accessible by the DMA controller and the flash-memory controller, for storing a current status of the data buffer, the current status being related to the data transfer;

wherein the DMA controller and the flash-memory controller are configured such that the DMA controller and the flash-memory controller are allowed to update the current status and to detect a change of the current status during the data transfer, so that a substantial part of the data transfer'"'"'s process is executed through direct interaction between the DMA controller and the flash-memory controller without involving a central processing unit.

2. The data-transfer subsystem of claim 1, further comprising a command storing unit configured to:

receive command packages, each of which includes an operation type specifying a command executable by the flash-memory controller, and is directed to a target flash memory module selected from the one or more flash memory modules;

store the command packages in one or more ordered sequences according to the target flash memory modules that the command packages are directed to, wherein the command packages stored in any of the one or more ordered sequences are arranged in order of the command packages'"'"' received times or received orders; and

allow the flash-memory controller to retrieve the command packages stored in a selected sequence one-by-one according to the selected sequence'"'"'s order, wherein the selected sequence is any one of the one or more ordered sequences.

3. The data-transfer subsystem of claim 2, wherein the command packages are received from the central processing unit.

4. The data-transfer subsystem of claim 2, wherein each of the command packages further includes:

a command-initiating value for indicating to the flash-memory controller to initiate execution of the command when the current status matches the command-initiating value;

a command-done value, with which the current status is updated by the flash-memory controller when the command is done;

an address of the target flash memory module;

an address of the data buffer if the command is related to a read operation or a write operation; and

a list of meta data for supporting execution of the command by the flash-memory controller.

5. The data-transfer subsystem of claim 2, wherein the command is related to an operation of Erase, Program, Read, Read Status, Reset, or Multi-Plane commands.

6. The data-transfer subsystem of claim 2, wherein the command storing unit comprises one or more command storing subunits each of which is configured to store the command packages in a unique ordered sequence selected from the one or more ordered sequences, the number of the one or more command storing subunits being equal to the number of the one or more flash memory modules.

7. The data-transfer subsystem of claim 1, wherein:

the data buffer comprises one or more constituent buffers each of which is for buffering data originated from or to be directed to a dedicated flash memory module selected from the one or more flash memory modules; and

the status-register group comprises one or more status registers each of which stores the current status of a unique constituent buffer selected from the one or more constituent buffers, the number of the one or more status registers being equal to the number of the one or more constituent buffers.

8. The data-transfer subsystem of claim 1, wherein each of the one or more flash memory modules is a NAND flash memory, a non-XIP (non-execute-in-place) memory, or a non-volatile flash storage medium.

9. The data-transfer subsystem of claim 1, wherein the data buffer is realized by a random access memory (RAM) or a plurality of RAMs, either single-port or dual-port.

10. The data-transfer subsystem of claim 1, wherein the flash-memory controller is dedicated to perform NAND flash commands, or commands in any other command set according to memory type.

11. The data-transfer subsystem of claim 1, wherein the subsystem is used in a SATA (Serial Advanced Technology Attachment) device or a USB (Universal Serial Bus) device or a PCIE (Peripheral Component Interconnect Express) device or any other device.

12. A method for enabling data transfer between a host memory and a flash memory module through direct memory access (DMA), a DMA controller being used for transferring data to and from the host memory, a flash-memory controller being used for transferring data to and from the flash memory module, a data buffer being used for buffering data transferred between the DMA controller and the flash-memory controller, the method comprising:

when a host command related to transferring data between the host memory and the flash memory module is received, configuring, by a central processing unit, the DMA controller and the flash-memory controller to carry out the host command, wherein the central processing unit configures the flash-memory controller by generating one or more command packages arranged as an ordered sequence for sequential execution by the flash-memory controller;

sequentially executing, by the flash-memory controller, the one or more command packages one-by-one according to the ordered sequence'"'"'s order until all the one or more command packages are executed, wherein before execution of a first command package selected from the one or more command packages is complete, execution of a second command package that follows the first command package is not initiated;

configuring the DMA controller and the flash-memory controller to check and update a current status of the data buffer, the current status being related to the data transfer, such that;

during the execution of the first command package, if the current status checked by the flash-memory controller does not match a first value, the flash-memory controller waits until the DMA controller updates the current status with the first value; and

when the execution of the first command package is complete, the flash-memory controller updates the current status with a second value, such that completion of the execution of the first command package is detectable by the DMA controller upon checking the current status;

so as to enable direct interaction between the DMA controller and the flash-memory controller without involving the central processing unit in executing a substantial part of the data transfer'"'"'s process.

13. The method of claim 12, wherein:

the first value is a command-initiating value provided in the first command package; and

the second value is a command-done value provided in the first command package.

14. The method of claim 12, further comprising:

after generating the one or more command packages, storing, by the central processing unit, all the one or more command packages to a command storing unit, thereby allowing the flash-memory controller to retrieve the one or more command packages for sequential execution directly from the command storing unit without a need to further involve the central processing unit.

15. The method of claim 12, wherein each of the command packages includes:

an operation type specifying a command executable by the flash-memory controller;

a command-initiating value for indicating to the flash-memory controller to initiate execution of the command when the current status matches the command-initiating value;

a command-done value, with which the current status is updated by the flash-memory controller when the command is done;

an address of the flash memory module;

an address of the data buffer if the command is related to a read operation or a write operation; and

a list of meta data for supporting execution of the command by the flash-memory controller.

16. The method of claim 15, wherein the command is related to an operation of Erase, Program, Read, Read Status, Reset, or Multi-Plane commands.

17. The method of claim 12, wherein the flash memory module is a NAND flash memory, a non-XIP (non-execute-in-place) memory, or a non-volatile flash storage medium.

18. The method of claim 12, wherein the data buffer is realized by a random access memory (RAM) or a plurality of RAMs, either single-port or dual-port.

19. The method of claim 12, wherein the flash-memory controller is dedicated to perform NAND flash commands, or commands in any other command set according to memory type.

20. The method of claim 12, wherein the method is used for a SATA (Serial Advanced Technology Attachment) device or a USB (Universal Serial Bus) device or a PCIE (Peripheral Component Interconnect Express) device or any other device.