MEMORY SYSTEM WITH USER CONFIGURABLE DENSITY/PERFORMANCE OPTION

• US 20140149648A1
• Filed: 01/30/2014
• Published: 05/29/2014
• Est. Priority Date: 06/04/2004
• Status: Abandoned Application

• Current Assignee: Micron Technology, Inc.
• Original Assignee: Micron Technology, Inc.
• Inventors: Roohparvar, Frankie F.
• Application Number:
  US14/168,407
• Publication Number:
  US 20140149648A1
• Time in Patent Office: Days
• US Class Current: 711/103
• CPC Class Codes: G06F 12/0246 in block erasable memory, e.g. flash memory
• CPC Class Codes: G11C 11/5621 using charge storage in a floating gate
• CPC Class Codes: G11C 16/0483 comprising cells having several storage transistors connected in series
• CPC Class Codes: G11C 2211/5641 Multilevel memory having cells with different number of storage levels

Abstract

The memory system has one or more memory dies coupled to a processor or other system controller. Each die has a separate memory array organized into multiple memory blocks. The different memory blocks of each die can be assigned a different memory density by the end user, depending on the desired memory performance and/or memory density. The user configurable density/performance option can be adjusted with special read/write operations or a configuration register having a memory density configuration bit for each memory block.

Claims

1. An apparatus comprising:

a memory array comprising a block of memory cells;

control circuitry configured to control operations on the memory array; and

a configuration register coupled to the control circuitry and configured to store a density configuration bit, wherein the density configuration bit is assigned to a sub-block of the block of memory cells and wherein the block of memory cells is assigned multiple configuration bits.

2. The apparatus of claim 1, wherein a memory device includes the memory array, the control circuitry and the configuration register, and wherein the apparatus further comprises a processor coupled to the memory device.

3. The apparatus of claim 2, further comprising a random access memory (RAM) to store memory density configuration data that is read from the memory array.

4. The apparatus of claim 1, wherein the configuration register is configured to also store at least one of trimming data, memory block lock data, and record keeping data.

5. The apparatus of claim 1, wherein the configuration register is further configured to store another density configuration bit, wherein the other density configuration bit is assigned to more than one block of memory cells.

6. The apparatus of claim 1, wherein the control circuitry is configured to load configuration data from the memory array into the configuration register.

7. The apparatus of claim 1, wherein the control circuitry is configured to load configuration data from the memory array into the configuration register at initialization of a device including the memory array, the control circuitry and the configuration register.

8. The apparatus of claim 1, wherein the control circuitry is configured to load configuration data from the memory array into the configuration register at power-tip of a device including the memory array, the control circuitry and the configuration register.

9. The apparatus of claim 1, wherein the control circuitry is configured to check the configuration register to determine a configuration assignment of the block.

10. The apparatus of claim 1, wherein the control circuitry is configured to copy data in the configuration register to the memory array in relation to powering down of a device including the memory array, the control circuitry and the configuration register.

11. An apparatus comprising:

a memory array comprising a block of memory cells;

control circuitry configured to control operations on the memory array, the control circuitry configured to set memory blocks of the memory to one of a high density configuration or a low density configuration to achieve a desired reliability indicator.

12. The apparatus of claim 11, wherein a memory device includes the memory array, the control circuitry and the configuration register, and wherein the apparatus further comprises a processor coupled to the memory device.

13. The apparatus of claim 11, wherein the desired reliability indicator is a mean time before failure.

14. The apparatus of claim 11, wherein the desired reliability indicator is a range mean times before failure.

15. The apparatus of claim 11, and further comprising a table stored in the memory, the table configured to contain entries indicating a quantity of memory blocks that are to be set to the high density configuration and the low density configuration in order to achieve the desired reliability indicator.

16. The apparatus of claim 11, and further comprising a table stored in the memory, the table configured to store density configuration bits for memory blocks of the memory having the high density configuration and the low density configuration.

17. The apparatus of claim 11, and further comprising a configuration register coupled to the control circuitry, the configuration register configured to store a configuration bit indicating an operating mode for each memory block of the memory.

18. The apparatus of claim 11, and further comprising a configuration register coupled to the control circuitry, the configuration register configured to store a plurality of configuration bits, and wherein a configuration bit of the configuration register is configured to store density configuration information for more than one block of memory cells of the memory array.

19. An apparatus comprising:

a memory array comprising a block of memory cells;

control circuitry configured to control operations on the memory array; and

a configuration register coupled to the control circuitry and configured to store density configuration bits to set memory blocks of the memory to one of a high density configuration or a low density configuration to achieve a desired reliability indicator.

20. The apparatus of claim 19, wherein a memory device includes the memory array, the control circuitry and the configuration register, and wherein the apparatus further comprises a processor coupled to the memory device.