LOW LATENCY DATA EXCHANGE

• US 20140149673A1
• Filed: 03/06/2013
• Published: 05/29/2014
• Est. Priority Date: 11/27/2012
• Status: Active Grant

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: Fleischer, Bruce M., Fox, Thomas W., Jacobson, Hans M., Nair, Ravi
• Granted Patent: US 9,268,704 B2
• Time in Patent Office: Days
• US Class Current: 711/133
• CPC Class Codes: G06F 12/0888 using selective caching, e.g. bypass
• CPC Class Codes: Y02D 10/00 Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

According to one embodiment, a method for exchanging data in a system that includes a main processor in communication with an active memory device is provided. The method includes a processing element in the active memory device receiving an instruction from the main processor and receiving a store request from a thread running on the main processor, the store request specifying a memory address associated with the processing element. The method also includes storing a value provided in the store request in a queue in the processing element and the processing element performing the instruction using the value from the queue.

Claims

1. A system for exchanging data, the system comprising:

a main processor in communication with an active memory device, the method comprising;

receiving, at a processing element in the active memory device, an instruction from the main processor;

receiving, at the processing element, a store request from a thread running on the main processor, the store request specifying a memory address associated with the processing element;

storing a value provided in the store request in a queue in the processing element; and

performing, by the processing element, the instruction using the value from the queue.

2. The system of claim 1, wherein storing the value comprises storing an 8 byte value or a 16 byte value.

3. The system of claim 1, wherein storing the value, performing the instruction are synchronized based on a predetermined code execution on both the processing element and the main processor.

4. The system of claim 3, wherein the predetermined code execution is determined by a compiler when compiling an application that has code that executes on both the processing element and the main processor.

5. The system of claim 1, wherein receiving the store request from the thread running on the main processor further comprises receiving a store request from the main processor that bypasses all system cache before it is received by the processing element.

6. The system of claim 1, wherein receiving the store request from the thread running on the main processor further comprises receiving a push request to push the value to the queue.

7. The system of claim 1, wherein storing the value provided in the store request in the queue further comprises storing the value in a shared queue that is used for both store and load requests.

8. The system of claim 1, wherein storing the value provided in the store request in the queue further comprises storing the value in a queue entry identified by a processor head pointer, wherein the processor head pointer moves to a subsequent entry after storing the value in the queue entry.

9. A system for exchanging data, the system comprising:

a main processor in communication with an active memory device, the method comprising;

receiving, at a processing element in the active memory device, an instruction from the main processor;

receiving, at the processing element, a load request from a thread running on the main processor, the load request specifying a memory address associated with the processing element;

placing tag information relating to the load request in a queue in the processing element;

performing, by the processing element, the instruction;

placing a result of the instruction in the queue; and

communicating, by the processing element, the result to the main processor in response to the load request, wherein communicating the result comprises bypassing all system cache before it is received by the main processor.

10. The system of claim 9, wherein placing the result of the instruction in the queue comprises placing the result in a shared queue that is used for both store and load requests.

11. The system of claim 9, wherein placing the result of the instruction in the queue comprises placing an 8 byte result value or a 16 byte result value in the queue.

12. The system of claim 9, wherein placing tag information relating to the load request in the queue, performing the instruction, and placing a result of the instruction in the queue are synchronized based on a predetermined code execution on both the processing element and the main processor.

13. The system of claim 12, wherein the predetermined code execution is determined by a compiler when compiling an application that has code execute on both the processing element and the main processor.

14. The system of claim 13, wherein the predetermined code execution comprises an in order execution wherein the result is placed in the queue without an identifier.

15. The system of claim 9, wherein receiving the load request from the thread running on the main processor further comprises receiving a load request that specifies the memory address associated with the processing element that will provide the result.

16. The system of claim 9, wherein receiving the load request from the thread running on the main processor further comprises receiving a load request from the main processor that bypasses all system cache before it is received by the processing element.

17. The system of claim 9, wherein placing the result of the instruction in the queue further comprises placing the result in a register file in the processing element and copying the result from the register file to the queue in the processing element.

18. The system of claim 9, wherein receiving the load request further comprises receiving a pull request to pull the result from the queue.

19. The system of claim 9, wherein placing tag information relating to the load request in the queue further comprises placing the tag information in an information entry in an information portion of the queue, wherein the information entry has a corresponding data entry in a data portion of the queue.

20. The system of claim 19, wherein placing the result of the instruction in the queue further comprises placing the result in the corresponding data entry identified by a processing element head pointer, wherein the processing element head pointer moves to a subsequent entry after placing the value in the corresponding data entry.