USING CACHE HIT INFORMATION TO MANAGE PREFETCHES

• US 20140149678A1
• Filed: 11/27/2012
• Published: 05/29/2014
• Est. Priority Date: 11/27/2012
• Status: Active Grant

• Current Assignee: NVIDIA Corporation
• Original Assignee: NVIDIA Corporation
• Inventors: Chaudhary, Anurag
• Granted Patent: US 9,262,328 B2
• Time in Patent Office: Days
• US Class Current: 711/137
• CPC Class Codes: G06F 12/0802 Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
• CPC Class Codes: G06F 12/0862 with prefetch
• CPC Class Codes: G06F 12/0897 with two or more cache hierarchy levels with multilevel cache hierarchies G06F12/0811
• CPC Class Codes: G06F 2212/6026 Prefetching based on access pattern detection, e.g. stride based prefetch

Abstract

Cache hit information is used to manage (e.g., cap) the prefetch distance for a cache. In an embodiment in which there is a first cache and a second cache, where the second cache (e.g., a level two cache) has greater latency than the first cache (e.g., a level one cache), a prefetcher prefetches cache lines to the second cache and is configured to receive feedback from that cache. The feedback indicates whether an access request issued in response to a cache miss in the first cache results in a cache hit in the second cache. The prefetch distance for the second cache is determined according to the feedback.

Claims

1. A system comprising:

a plurality of caches comprising first cache and a second cache, the second cache having greater latency than the first cache; and

a prefetcher configured to prefetch cache lines to the second cache and further configured to receive feedback from the second cache, the feedback indicating whether an access request issued in response to a cache miss in the first cache results in a cache hit in the second cache, wherein the cache lines prefetched to the second cache are selected according to a prefetch distance, the prefetch distance determined according to the feedback.

2. The system of claim 1 wherein the cache lines are selected for prefetching according to a pattern of cache misses in the second cache that occurred prior to the cache hit.

3. The system of claim 2 wherein the prefetch distance increases to a first value according to the pattern, wherein further the prefetch distance is held at the first value in response to the cache hit.

4. The system of claim 2 wherein the prefetch distance increases to a first value according to the pattern, wherein further the prefetch distance continues to increase after the cache hit until the prefetch distance reaches a second value that is larger than the first value by a specified margin.

5. The system of claim 2 wherein the prefetch distance increases to a first value according to a confidence level associated with the pattern, the confidence level comprising a value that increases as the pattern increases in length, and wherein the prefetch distance is held at the first value in response to the cache hit even if the confidence level increases.

6. The system of claim 1 wherein the prefetch distance has a maximum value, wherein the prefetch distance is held at a first value in response to the cache hit, the first value less than the maximum value.

7. The system of claim 1 wherein the prefetcher is further configured to prefetch cache lines to the first cache, wherein the feedback further indicates whether a demand request issued to the first cache results in a cache hit in the first cache.

8. A computer system comprising:

a processing unit;

a plurality of caches comprising a first cache and a second cache coupled to the processing unit, the second cache having greater latency than the first cache; and

memory coupled to the processing unit and having stored therein instructions that, if executed by the computer system, cause the computer system to execute a prefetcher that performs operations comprising;

prefetching cache lines to the second cache, wherein the cache lines are selected according to a prefetch distance;

receiving feedback from the second cache indicating whether an access request issued in response to a cache miss in the first cache results in a cache hit in the second cache; and

determining the prefetch distance according to the feedback.

9. The computer system of claim 8 wherein the operations performed by the prefetcher further comprise:

increasing the prefetch distance to a first value according to a pattern of cache misses in the second cache, wherein the cache misses occur prior to the cache hit in the second cache; and

maintaining the prefetch distance at the first value in response to the cache hit.

10. The computer system of claim 8 wherein the operations performed by the prefetcher further comprise increasing the prefetch distance to a first value according to a pattern of cache misses in the second cache, wherein the cache misses occur prior to the cache hit in the second cache, wherein further the prefetch distance continues to increase to greater than the first value after the cache hit until the prefetch distance reaches a second value that is larger than the first value by a specified margin.

11. The computer system of claim 10 wherein the operations performed by the prefetcher further comprise selecting the cache lines for prefetching according to the pattern and the prefetch distance.

12. The computer system of claim 11 wherein the first value corresponds to a confidence level associated with the pattern, the confidence level comprising a value that increases as the pattern increases in length, and wherein further the prefetch distance is not increased beyond the first value even if the confidence level increases in response to the cache hit.

13. The computer system of claim 8 wherein the prefetch distance has a maximum value, wherein the first value is less than the maximum value.

14. The computer system of claim 8 wherein the operations performed by the prefetcher further comprise prefetching cache lines to the first cache, wherein the feedback further indicates whether a demand request issued to the first cache results in a cache hit in the first cache.

15. A method implemented by a computer system comprising a processor, a memory, and a plurality of caches coupled to the processor and the memory and comprising a first cache and a second cache, the second cache having greater latency than the first cache, the method comprising:

prefetching cache lines into the second cache, wherein the cache lines are selected for prefetching using a prefetch distance that increases to a first value according to a pattern of cache misses in the second cache;

in response to a cache miss in the first cache, sending an access request to the second cache; and

if the access request results in a cache hit in the second cache, then capping the prefetch distance even if the pattern continues to increase in length.

16. The method of claim 15 wherein the prefetch distance is capped at a second value that is equal to the first value.

17. The method of claim 15 wherein the prefetch distance is capped at a second value that is larger than the first value by a specified margin, wherein the prefetch distance is allowed to increase after the cache hit until the second value is reached.

18. The method of claim 15 wherein the first value corresponds to a confidence level associated with the pattern, the confidence level comprising a value that increases as the pattern increases in length.

19. The method of claim 15 wherein the prefetch distance has a maximum value, wherein the prefetch distance is capped at a value that is less than the maximum value.

20. The method of claim 15 further comprising:

prefetching cache lines to the first cache; and

determining whether an access request issued to the first cache results in a cache hit in the first cache.