LOW LATENCY DATA EXCHANGE
First Claim
1. A method for exchanging data in a system that includes a main processor in communication with an active memory device, the method comprising:
- receiving, at a processing element in the active memory device, an instruction from the main processor;
receiving, at the processing element, a store request from a thread running on the main processor, the store request specifying a memory address associated with the processing element;
storing a value provided in the store request in a queue in the processing element; and
performing, by the processing element, the instruction using the value from the queue.
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Accused Products
Abstract
According to one embodiment, a method for exchanging data in a system that includes a main processor in communication with an active memory device is provided. The method includes a processing element in the active memory device receiving an instruction from the main processor and receiving a store request from a thread running on the main processor, the store request specifying a memory address associated with the processing element. The method also includes storing a value provided in the store request in a queue in the processing element and the processing element performing the instruction using the value from the queue.
40 Citations
28 Claims
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1. A method for exchanging data in a system that includes a main processor in communication with an active memory device, the method comprising:
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receiving, at a processing element in the active memory device, an instruction from the main processor; receiving, at the processing element, a store request from a thread running on the main processor, the store request specifying a memory address associated with the processing element; storing a value provided in the store request in a queue in the processing element; and performing, by the processing element, the instruction using the value from the queue. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8)
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9-16. -16. (canceled)
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17. A method for exchanging data in a system that includes a main processor in communication with an active memory device, the method comprising:
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receiving, at a processing element in the active memory device, an instruction from the main processor; receiving, at the processing element, a load request from a thread running on the main processor, the load request specifying a memory address associated with the processing element; placing tag information relating to the load request in a queue in the processing element; performing, by the processing element, the instruction; placing a result of the instruction in the queue; and communicating, by the processing element, the result to the main processor in response to the load request, wherein communicating the result comprises bypassing all system cache before it is received by the main processor. - View Dependent Claims (18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28)
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Specification