AT-SPEED INTEGRATED CIRCUIT TESTING USING THROUGH SILICON IN-CIRCUIT LOGIC ANALYSIS

• US 20140149811A1
• Filed: 04/12/2013
• Published: 05/29/2014
• Est. Priority Date: 04/12/2012
• Status: Active Grant

• Current Assignee: Semicaps Pte Limited
• Original Assignee: Larry Ross, Michael Bruce
• Inventors: Ross, Larry, Bruce, Michael
• Granted Patent: US 9,714,978 B2
• Time in Patent Office: Days
• US Class Current: 714/724
• CPC Class Codes: G01R 31/2882 Testing timing characteristics
• CPC Class Codes: G01R 31/311 of integrated circuits G01R31/31728 takes precedence

Abstract

A method, system, and computer program product for integrated circuit wafer and die testing. The method commences by selecting areas of interest accessible from a backside of an integrated circuit where the areas of interest correspond to electronic devices (e.g., gates or transistors or vias or pads). Then, using a small-beam light source such as a laser, illuminating the areas of interest and collecting the reflected signal returned from illuminated areas of interest. A processor analyses the reflected signal to determine logic states and timing information of the electronic devices and compares the determined logic states and timing information to a pre-determined logic pattern to identify one or more errors as observed from the actual electronic devices. Specific points within an area of interest are determined from CAD layout data, and the pre-determined logic patterns can be retrieved from CAD simulation data.

Claims

1. A method for testing an integrated circuit, the method comprising:

selecting a plurality of areas of interest on an integrated circuit that correspond to a plurality of electronic devices of the integrated circuit;

illuminating each of the areas of interest;

receiving a reflected signal from illumination of the areas of interest; and

analyzing the reflected signal to determine logic states and timing information of the electronic devices.

2. The method of claim 1, further comprising comparing the logic states and timing information to a pre-determined logic pattern to determine one or more errors in the electronic devices.

3. The method of claim 1, wherein the areas of interest are determined using CAD data.

4. The method of claim 1, wherein successive areas of interest are not adjacent.

5. The method of claim 1, wherein the areas of interest are determined using user-supplied data.

6. The method of claim 1, wherein illuminating each of the areas of interest comprises positioning an XY stage.

7. The method of claim 1, further comprising successively illuminating and analyzing to determine a time-based logic pattern.

8. The method of claim 7, further comprising displaying, using one or more display surfaces, the time-based logic pattern.

9. A system for testing an integrated circuit, comprising:

a processor to execute a set of program code instructions; and

a memory to hold the program code instructions, in which the program code instructions comprises program code to perform; and

sampling digitizer with memory buffer such that digitizer can continuously sample data without interruption,

selecting a plurality of areas of interest on an integrated circuit that correspond to a plurality of electronic devices of the integrated circuit;

illuminating each of the areas of interest;

receiving a reflected signal from illumination of the areas of interest; and

analyzing the reflected signal to determine logic states and timing information of the electronic devices.

10. The system of claim 9, further comprising program code for comparing the logic states and timing information to a pre-determined logic pattern to determine one or more errors in the electronic devices.

11. The system of claim 9, wherein the areas of interest are determined using CAD data.

12. The system of claim 9, wherein successive areas of interest are not adjacent.

13. The system of claim 9, wherein the areas of interest are determined using user-supplied data.

14. The system of claim 9, wherein illuminating each of the areas of interest comprises positioning an XY stage.

15. The system of claim 9, further comprising program code for successively illuminating and analyzing to determine a time-based logic pattern.

16. The system of claim 15, further comprising program code for displaying, using one or more display surfaces, the time-based logic pattern.

17. A computer program product embodied in a non-transitory computer readable medium, the computer readable medium having stored thereon a sequence of instructions which, when executed by a processor causes the processor to execute a process for testing an integrated circuit, the process comprising:

selecting a plurality of areas of interest on an integrated circuit that correspond to a plurality of electronic devices of the integrated circuit;

illuminating each of the areas of interest;

receiving a reflected signal from illumination of the areas of interest; and

analyzing the reflected signal to determine logic states and timing information of the electronic devices.

18. The computer program product of claim 17, further comprising instructions for comparing the logic states and timing information to a pre-determined logic pattern to determine one or more errors in the electronic devices.

19. The computer program product of claim 18, further comprising instructions for autocorrelation analysis to determine probability of a match to the pre-determined logic pattern.

20. The computer program product of claim 17, wherein the areas of interest are determined using CAD data.

21. The computer program product of claim 17, wherein the areas of interest are determined using user-supplied data.

22. The computer program product of claim 17, wherein successive areas of interest are not adjacent.

23. The computer program product of claim 17, further comprising instructions for successively illuminating and analyzing to determine a time-based logic pattern.

24. The computer program product of claim 17, further comprising instructions for determining a Schmoo plot or graphical representation of selective test parameters.

25. The computer program product of claim 17, further comprising instructions for cross referencing logic cell chains or cones to correlate as passing or failing.

26. The computer program product of claim 17, further comprising instructions for sampling Boolean logic for at least one of, thresholding, box car averaging, or edge enhancement.

27. The computer program product of claim 17, further comprising instructions for calculating a minimum number of samples to determine a passing state.