3D FLOORPLANNING USING 2D AND 3D BLOCKS

• US 20140149958A1
• Filed: 03/11/2013
• Published: 05/29/2014
• Est. Priority Date: 11/28/2012
• Status: Active Grant

• Current Assignee: Qualcomm, Inc.
• Original Assignee: Qualcomm, Inc.
• Inventors: Samadi, Kambiz, Panth, Shreepad A., Du, Yang
• Granted Patent: US 9,064,077 B2
• Time in Patent Office: Days
• US Class Current: 716/123
• CPC Class Codes: G06F 2115/08 Intellectual property [IP] blocks or IP cores
• CPC Class Codes: G06F 30/392 Floor-planning or layout, e.g. partitioning or placement

Abstract

The disclosed embodiments are directed to systems and method for floorplanning an integrated circuit design using a mix of 2D and 3D blocks that provide a significant improvement over existing 3D design methodologies. The disclosed embodiments provide better floorplan solutions that further minimize wirelength and improve the overall power/performance envelope of the designs. The disclosed methodology may be used to construct new 3D IP blocks to be used in designs that are built using monolithic 3D integration technology.

Claims

1. A method of generating a library of blocks to be floorplanned, the steps comprising:

assembling, by a computing device, a plurality of blocks comprising 2D implementations and 3D implementations;

providing a first additional tier for at least one of the plurality of blocks and generating a first re-implementation of the at least one of the plurality of blocks that includes first additional tier;

evaluating at least one performance objective of the first re-implementation to determine whether the at least one performance objective has improved; and

adding the first re-implementation to the library of blocks to be floorplanned if a result of the evaluating step is that said at least one performance objective has improved,

wherein the library of blocks to be floorplanned comprises a library of 3D monolithic blocks, wherein at least one 3D monolithic block includes one or more electronic components built sequentially in two or more layers on a single semiconductor wafer.

2. The method of claim 1, further comprising the steps of:

if the at least one performance parameter improved, providing a second additional tier for the at least one of the plurality of blocks and generating a second reimplementation of the at least one of the plurality of blocks that includes the second additional tier;

further evaluating the at least one performance objective for the second re-implementation to determine whether at least one performance objective has improved; and

adding the second re-implementation to the library of 3D monolithic blocks to be floorplanned if a result of further evaluating step is that the at least one performance objective has improved.

11. The method of claim 1, wherein at least one of the 3D monolithic block includes at least one electronic component on a single semiconductor wafer.

12. The method of claim 11, wherein the single semiconductor wafer is diced into 3D integrated circuits (ICs).

3. The method of 2, further comprising the steps of floorplanning the library of 3D monolithic blocks.

6. The method of claim 3, wherein the step of floorplanning the library of 3D monolithic blocks results in an IP block that may be used for a larger design that includes the IP block.

7. The method of claim 6, wherein the step of floorplanning the library of 3D monolithic blocks results in a monolithic 3D floorplan having a network of high density vias.

8. The method of claim 7, wherein the network of high density vias comprises inter-tier vias.

9. The method of claim 3, wherein the step of floorplanning the library of 3D monolithic blocks comprises floorplanning the library of 3D monolithic blocks using a simulated annealing 3D floorplan engine.

10. The method of claim 3, further comprising determining pin assignments for the library of 3D monolithic blocks, wherein pin assignments are determined by:

determining whether the floorplan comprises a hard macro;

accepting existing pin assignments if the floorplan comprises a hard macro; and

if the floor plan comprises a soft macro allowing pins to be on each tier of the floorplan and fixing a location of the pins using 2D partitioning methodologies.

4. (canceled)

5. (canceled)

13. An integrated circuit floorplan, comprising:

at least one 3D block; and

at least one 2D block coupled to the at least one 3d block.

14. The integrated circuit floorplan of claim 13, further comprising:

a first tier; and

a second tier coupled to the first tier.

15. The integrated circuit floorplan of claim 14, wherein the at least one 3D block spans the first tier and the second tier.

16. The integrated circuit floorplan of claim 15, wherein the at least one 2D block is distributed on the first tier.

17. The integrated circuit floorplan of claim 15, wherein the at least one 2D block is distributed on the second tier.

18. The integrated circuit floorplan of claim 14, further comprising a network of vias coupling the first tier to the second tier.

20. The non-transitory computer-readable storage medium of claim 15, further including data that, when accessed by the machine, cause the machine to perform operations of:

if the at least one performance parameter improved, providing a second additional tier for the at least one of the plurality of blocks and generating a second reimplementation of the at least one of the plurality of blocks that includes the second additional tier;

further evaluating the at least one performance objective for the second re-implementation to determine whether at least one performance objective has improved; and

adding the second re-implementation to the library of 3D monolithic blocks to be floorplanned if a result of further evaluating step is that the at least one performance objective has improved.

19. A non-transitory computer-readable storage medium including data that, when accessed by a machine, cause the machine to perform operations comprising:

assembling, by a computing device, a plurality of blocks comprising 2D implementations and 3D implementations;

providing a first additional tier for at least one of the plurality of blocks and generating a first re-implementation of the at least one of the plurality of blocks that includes first additional tier;

evaluating at least one performance objective of the first re-implementation to determine whether the at least one performance objective has improved; and

adding the first re-implementation to the library of blocks to be floorplanned if a result of the evaluating step is that at least one performance objective has improved,

wherein the library of blocks to be floorplanned comprises a library of 3D monolithic blocks, wherein at least one 3D monolithic block includes one or more electronic components built sequentially in two or more layers on a single semiconductor wafer.