Packaged Vertical Power Device Comprising Compressive Stress and Method of Making a Packaged Vertical Power Device

• US 20140151717A1
• Filed: 12/04/2012
• Published: 06/05/2014
• Est. Priority Date: 12/04/2012
• Status: Active Grant

• Current Assignee: Infineon Technologies AG
• Original Assignee: Infineon Technologies AG
• Inventors: Otremba, Ralf
• Granted Patent: US 9,093,437 B2
• Time in Patent Office: Days
• US Class Current: 257/77
• CPC Class Codes: H01L 21/50 Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
• CPC Class Codes: H01L 2224/05644 Gold [Au] as principal constituent
• CPC Class Codes: H01L 2224/32245 the item being metallic
• CPC Class Codes: H01L 2224/45015 being circular
• CPC Class Codes: H01L 2224/45144 Gold (Au) as principal constituent
• CPC Class Codes: H01L 2224/48091 Arched
• CPC Class Codes: H01L 2224/48247 connecting the wire to a bond pad of the item
• CPC Class Codes: H01L 2224/73265 Layer and wire connectors
• CPC Class Codes: H01L 2224/85099 Ambient temperature
• CPC Class Codes: H01L 2224/854 with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
• CPC Class Codes: H01L 23/49513 having bonding material between chip and die pad
• CPC Class Codes: H01L 23/49562 for devices being provided for in H01L29/00
• CPC Class Codes: H01L 23/49575 Assemblies of semiconductor devices on lead frames
• CPC Class Codes: H01L 29/1608 Silicon carbide
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00012 Relevant to the scope of the group, the symbol of which is combined with the symbol of this group
• CPC Class Codes: H01L 2924/00014 the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/1305 Bipolar Junction Transistor [BJT]
• CPC Class Codes: H01L 2924/13055 Insulated gate bipolar transistor [IGBT]
• CPC Class Codes: H01L 2924/13062 Junction field-effect transistor [JFET]
• CPC Class Codes: H01L 2924/13091 : Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]
• CPC Class Codes: H01L 2924/181 : Encapsulation
• CPC Class Codes: H01L 2924/20751 : larger or equal to 10 microns less than 20 microns
• CPC Class Codes: H01L 2924/20752 : larger or equal to 20 microns less than 30 microns
• CPC Class Codes: H01L 2924/20753 : larger or equal to 30 microns less than 40 microns
• CPC Class Codes: H01L 2924/20754 : larger or equal to 40 microns less than 50 microns
• CPC Class Codes: H01L 2924/20755 : larger or equal to 50 microns less than 60 microns
• CPC Class Codes: H01L 2924/3025 : Electromagnetic shielding
• CPC Class Codes: H01L 2924/3511 : Warping

Abstract

A packaged vertical semiconductive device including a compressive stress and a method of making such a packaged vertical semiconductive device are disclosed. In one embodiment an assembled device includes a carrier, a connection layer disposed on the carrier, the connection layer having a first height, and a chip disposed on the connection layer, the chip having a second height, wherein the second height is smaller than the first height.

Claims

1. An assembled device comprising:

a carrier;

a connection layer disposed on the carrier, the connection layer comprising a first height; and

a chip disposed on the connection layer, the chip comprising a second height,

wherein the second height is smaller than the first height.

2. The assembled device according to claim 1, wherein the second height is equal or less than 40 μ

m and wherein the first height is equal to or greater than 40 μ

m.

3. The assembled device according to claim 2, wherein the connection layer comprises a conductive adhesive paste.

4. The assembled device according to claim 2, wherein the connection layer comprises a conductive adhesive foil.

5. The assembled device according to claim 2, wherein the connection layer comprises a soft solder.

6. The assembled device according to claim 1, wherein the second height is equal to or less than 5 μ

m and wherein the first height is equal to or greater than 5 μ

m.

7. The assembled device according to claim 6, wherein the connection layer comprises a diffusion solder layer.

8. The assembled device according to claim 1, wherein the connection layer is a backside metallization layer (BSM).

9. The assembled device according to claim 1, the chip is a vertical power semiconductor device comprising a compressive stress.

10. The assembled device according to claim 1, wherein the chip comprises silicon carbide (SiC).

11. A packaged power device comprising:

a leadframe;

a connection layer disposed on a carrier;

a vertical power semiconductor chip disposed on the connection layer, wherein the vertical power semiconductor chip comprises a compressive stress over an entire height;

interconnects connecting chip contact pads to leads of the leadframe; and

an encapsulation encapsulating the vertical power semiconductor chip.

12. The packaged power device according to claim 11, wherein the compressive stress is equal to or greater than 100 MPa.

13. The packaged power device according to claim 11, wherein the vertical power semiconductor chip is equal to or less than 40 μ

m.

14. The packaged power device according to claim 13, wherein the connection layer comprises a soft solder layer, a conductive adhesive foil or a conductive adhesive paste, and wherein the connection layer comprises a height of equal to or greater than 40 μ

m.

15. The packaged power device according to claim 11, wherein the vertical power semiconductor chip is equal to or less than 10 μ

m.

16. The packaged power device according to claim 15, wherein the connection layer comprises a diffusion solder layer, and wherein the diffusion solder layer comprises a height of equal to or less than 10 μ

m.

17. The packaged power device according to claim 11, wherein a CTE of the leadframe is greater than 15 ppm/K and wherein a CTE of a substrate of the power semiconductor chip is between 2 ppm/K and 7 ppm/K.

18. A method of manufacturing a semiconductor device, the method comprising:

placing a vertical semiconductor device with a bottom main surface on a leadframe; and

connecting the semiconductor device via a connection layer to the leadframe thereby forming a compressive stress over an entire height of the semiconductor device, the connection layer being thicker than the semiconductor device.

19. The method according to claim 18, further comprising thinning the semiconductor device before placing the semiconductor device on the leadframe.

20. The method according to claim 18, wherein the vertical semiconductor device is a vertical power semiconductor device comprising a height of equal to or less than 40 μ

m.