SUBSTRATE-TEMPLATED EPITAXIAL SOURCE/DRAIN CONTACT STRUCTURES

• US 20140151757A1
• Filed: 12/03/2012
• Published: 06/05/2014
• Est. Priority Date: 12/03/2012
• Status: Abandoned Application

• Current Assignee: GlobalFoundries, Inc.
• Original Assignee: International Business Machines Corporation
• Inventors: Basu, Anirban, Chang, Josephine B., Guillorn, Michael A., Majumdar, Amlan
• Application Number:
  US13/692,162
• Publication Number:
  US 20140151757A1
• Time in Patent Office: Days
• US Class Current: 257/288
• CPC Class Codes: B82Y 40/00 Manufacture or treatment of nanostructures
• CPC Class Codes: H01L 21/76 Making of isolation regions between components
• CPC Class Codes: H01L 21/76264 SOI together with lateral isolation, e.g. using local oxidation of silicon, or dielectric or polycristalline material refilled trench or air gap isolation regions, e.g. completely isolated semiconductor islands
• CPC Class Codes: H01L 29/0673 oriented parallel to a substrate
• CPC Class Codes: H01L 29/42392 fully surrounding the channel, e.g. gate-all-around
• CPC Class Codes: H01L 29/66439 with a one- or zero-dimensional channel, e.g. quantum wire FET, in-plane gate transistor [IPG], single electron transistor [SET], striped channel transistor, Coulomb blockade transistor with an active layer made of a group 13/15 material H01L29/66469
• CPC Class Codes: H01L 29/775 with one dimensional charge carrier gas channel, e.g. quantum wire FET
• CPC Class Codes: H01L 29/78696 characterised by the structure of the channel, e.g. multichannel, transverse or longitudinal shape, length or width, doping structure, or the overlap or alignment between the channel and the gate, the source or the drain, or the contacting structure of the channel H01L29/78612 takes precedence; transistors having a drain offset region or a lightly doped drain [LDD] H01L29/78621

Abstract

Single crystalline semiconductor fins are formed on a single crystalline buried insulator layer. After formation of a gate electrode straddling the single crystalline semiconductor fins, selective epitaxy can be performed with a semiconductor material that grows on the single crystalline buried insulator layer to form a contiguous semiconductor material portion. The thickness of the deposited semiconductor material in the contiguous semiconductor material portion can be selected such that sidewalls of the deposited semiconductor material portions do not merge, but are conductively connected to one another via horizontal portions of the deposited semiconductor material that grow directly on a horizontal surface of the single crystalline buried insulator layer. Simultaneous reduction in the contact resistance and parasitic capacitance for a fin field effect transistor can be provided through the contiguous semiconductor material portion and cylindrical contact via structures.

Claims

1. A method of forming a semiconductor structure comprising:

forming at least one semiconductor material portion on a single crystalline dielectric layer;

forming a gate electrode straddling said at least one semiconductor material portion; and

forming a contiguous single crystalline semiconductor portion directly on an end subportion of each of said at least one semiconductor material portion by depositing a semiconductor material in epitaxial alignment with said single crystalline dielectric layer.

2. The method of claim 1, wherein said at least one semiconductor material portion has a doping of a first conductivity type, and said method further comprises doping said end subportion of each of said at least one semiconductor material portion with dopants of a second conductivity type that is the opposite of said first conductivity type.

3. The method of claim 1, further comprising recessing a portion of a top surface of said single crystalline dielectric layer, wherein said contiguous single crystalline semiconductor portion is formed directly on said recessed portion of said top surface of said single crystalline dielectric layer.

4. The method of claim 1, wherein said at least one semiconductor material portion is a plurality of semiconductor fins having parallel vertical sidewalls.

5. The method of claim 4, wherein each of said plurality of semiconductor fins is single crystalline and is in epitaxial alignment with said single crystalline dielectric layer.

6. The method of claim 5, further comprising forming a shallow trench isolation structure on said single crystalline dielectric layer, wherein vertical surfaces of said at least one semiconductor material portion contact said shallow trench isolation structure.

7. The method of claim 6, wherein each of said at least one semiconductor material portion extends along a horizontal lengthwise direction, has a substantially rectangular vertical cross-sectional shape within vertical planes perpendicular to said horizontal lengthwise direction.

8. The method of claim 6, further comprising:

forming a gate spacer laterally around said gate electrode; and

removing physically exposed portions of said at least one semiconductor portion that are not covered by said gate electrode or said gate spacer, wherein end surfaces of said at least one semiconductor portion are vertically coincident with outer sidewalls of said gate spacer after said removal of said physically exposed portions.

9. The method of claim 1, wherein said at least one semiconductor material portion is a plurality of semiconductor nanowires.

10. The method of claim 9, further comprising forming a first semiconductor pad and a second semiconductor pad over said single crystalline dielectric layer, wherein each first end of said semiconductor nanowire is attached to said first semiconductor pad, and each second end of said semiconductor nanowire is attached to said second semiconductor pad.

11. The method of claim 9, further comprising

forming a plurality semiconductor fins laterally contacting said first and second semiconductor pads;

removing portions of said single crystalline dielectric layer from underneath said plurality of semiconductor fins; and

converting said plurality of semiconductor fins into a plurality of semiconductor nanowires by an anneal.

12. The method of claim 9, wherein said gate electrode wraps around each of said plurality of semiconductor nanowires.

13. The method of claim 9, wherein said plurality of semiconductor nanowires extends along a horizontal lengthwise direction, and has a uniform vertical cross-sectional shape along said horizontal lengthwise direction.

14. A semiconductor structure comprising:

a substrate including a single crystalline dielectric layer;

at least one semiconductor material portion located on said single crystalline dielectric layer;

a gate electrode straddling said at least one semiconductor material portion; and

a contiguous single crystalline semiconductor portion contacting an end subportion of each of said at least one semiconductor material portion and having a single crystalline structure in epitaxial alignment with said single crystalline dielectric layer.

15. The semiconductor structure of claim 14, wherein a subportion of each of said at least one semiconductor material portion underlying said gate electrode has a doping of a first conductivity type, and said end subportion of each of said at least one semiconductor material portion has a doping of a second conductivity type that is the opposite of said first conductivity type.

16. The semiconductor structure of claim 14, wherein each of said at least one semiconductor material portion is single crystalline, and is in epitaxial alignment with said single crystalline dielectric layer.

17. The semiconductor structure of claim 14, wherein said at least one semiconductor material portion is a plurality of semiconductor material portions.

18. The semiconductor structure of claim 14, wherein a top surface of a bottom subportion of said contiguous single crystalline semiconductor portion is located below a topmost surface of said at least one semiconductor material portion.

19. The semiconductor structure of claim 14, further comprising a shallow trench isolation structure located above said single crystalline dielectric layer and laterally surrounding said at least one semiconductor material portion.

20. The semiconductor structure of claim 14, wherein said at least one semiconductor material portion is a plurality of semiconductor fins having parallel vertical sidewalls.

21. The semiconductor structure of claim 20, wherein each of said plurality of semiconductor fins is single crystalline and is in epitaxial alignment with said single crystalline dielectric layer.

22. The semiconductor structure of claim 14, wherein said at least one semiconductor material portion is a plurality of semiconductor nanowires.

23. The semiconductor structure of claim 22, wherein each first end of said semiconductor nanowire is attached to a first semiconductor pad, and each second end of said semiconductor nanowire is attached to a second semiconductor pad.

24. The semiconductor structure of claim 23, wherein a bottommost surface of said plurality of semiconductor nanowires is located above a topmost surface of said single crystalline dielectric layer.

25. The semiconductor structure of claim 23, wherein said plurality of semiconductor nanowires extends along a horizontal lengthwise direction, and has a uniform vertical cross-sectional shape along said horizontal lengthwise direction.