NAND FLASH MEMORY WITH VERTICAL CELL STACK STRUCTURE AND METHOD FOR MANUFACTURING SAME

• US 20140151774A1
• Filed: 03/14/2013
• Published: 06/05/2014
• Est. Priority Date: 12/04/2012
• Status: Active Grant

• Current Assignee: Conversant Intellectual Property Management Inc (MOSAID Technologies Inc. (f/k/a Conversant Intellectual Property Management))
• Original Assignee: MOSAID Technologies Inc. (f/k/a Conversant Intellectual Property Management)
• Inventors: Rhie, Hyoung Seub
• Granted Patent: US 10,403,766 B2
• Time in Patent Office: Days
• US Class Current: 257/314
• CPC Class Codes: G11C 11/5621 using charge storage in a floating gate
• CPC Class Codes: G11C 16/0483 comprising cells having several storage transistors connected in series
• CPC Class Codes: G11C 2213/71 Three dimensional array
• CPC Class Codes: H01L 29/66833 with a charge trapping gate insulator, e.g. MNOS transistors
• CPC Class Codes: H01L 29/7926 Vertical transistors, i.e. transistors having source and drain not in the same horizontal plane
• CPC Class Codes: H10B 43/27 the channels comprising vertical portions, e.g. U-shaped channels
• CPC Class Codes: H10B 43/40 characterised by the peripheral circuit region

Abstract

Disclosed is a method of manufacturing flash memory with a vertical cell stack structure. The method includes forming source lines in a cell area of a substrate having an ion-implanted well and forming an alignment mark relative to the source lines. The alignment mark is formed in the substrate outside the cell area of the substrate. After formation of the source lines, cell stacking layers are formed. After forming the cell stacking layers, cell pillars in the cell stacking layers are formed at locations relative to the previously formed source lines using the alignment mark to correctly locate the cell pillars.

Claims

1. A method of manufacturing flash memory with a vertical cell stack structure, the method comprising:

forming source lines in a cell area of a substrate having an ion-implanted well and forming an alignment mark relative to the source lines, the alignment mark being formed in the substrate outside the cell area of the substrate;

after formation of the source lines, forming cell stacking layers; and

after forming the cell stacking layers, forming cell pillars in the cell stacking layers at locations relative to the previously formed source lines using the alignment mark to correctly locate the cell pillars.

2. The method of claim 1 wherein forming cell pillars comprises:

forming a respective pillar hole for each cell pillar; and

forming a pillar body in each pillar hole, wherein each pillar body is formed in such a manner that during an erase operation of a flash memory produced using the method, the pillar body and the ion-implanted well form a single node.

3. The method of claim 1 wherein each cell pillar has a pillar body that is p-type material, and the ion-implanted well is p-type material.

4. The method of claim 1 wherein the source lines and the position of the alignment mark are defined as part of a single photolithography mask step.

5. The method of claim 1 further comprising forming bitlines parallel to the source lines and wordlines perpendicular to the source lines.

6. The method of claim 5 wherein forming wordlines comprises:

performing etching to define a pattern of alternating fins and slits; and

filling the slits with an isolating dielectric.

7. The method of claim 5 further comprising:

doping a top part of each cell pillar to function as a drain of the pillar.

8. The method of claim 7 wherein forming bitlines comprises:

applying bitlines using a metallization process so as to form electrical connections to the drain of each pillar.

9. The method of claim 1 wherein forming source lines and forming the alignment mark comprise:

performing etching to form trenches between where the source lines are to be located and to define the position of the alignment mark;

filling the trenches and alignment mark with a dielectric to form non-conductive trenches;

performing ion implantation and annealing to form conductive regions between the non-conductive trenches thereby forming the source lines;

or

performing ion implantation and annealing to form a conductive layer;

performing etching to form trenches between where the source lines are to be formed and to define the position of the alignment mark;

filling the trenches and the alignment mark with a dielectric material to form non-conductive trenches;

wherein regions of the conductive layer between the non-conductive trenches are the source lines.

10. The method of claim 9 wherein forming cell pillars comprises:

etching pillar holes in a column and row pattern such that the holes are formed on regions where the dielectric material fills the trenches.

11. The method of claim 9 wherein the holes are etched through the cell stacking layers but not the dielectric material;

the method further comprising;

depositing at least one gate dielectric layer;

performing another etch to extend each pillar hole through the dielectric material over which the pillar hole exists to the ion-implanted well of the substrate;

forming a pillar body in each pillar hole, wherein each pillar body is formed in such a manner that during an erase operation of a flash memory produced using the method, the pillar body and the ion-implanted well form a single node.

12. The method of claim 1 wherein forming source lines and forming the alignment mark comprises:

performing a first photolithography mask step that does not include etching the substrate to form the source lines in the ion-implanted well in the cell area and to define a location of the alignment mark;

subsequent to forming the source lines, performing at least one further photolithography mask step to complete formation of the alignment mark.

13. The method of claim 12 wherein performing a first photolithography mask step comprises:

applying a hard mask material which has a different etch selectivity than the ion-implanted well;

etching the hard mask to expose the ion-implanted well in regions where the source lines are to be formed and to expose the location of the alignment mark in an area outside the cell area;

performing ion implantation in exposed regions; and

performing at least one further photolithography mask step comprises;

etching a pattern in the ion-implanted substrate at the location of the alignment mark region but not in the cell area.

14. The method of claim 12 wherein:

performing a first photolithography mask step comprises;

applying a hard mask material which has a different etch selectivity than the substrate;

applying photoresist in a pattern that exposes regions where the source lines are to be formed and to define the location of the alignment mark in an area outside the cell area;

performing ion implantation through the hard mask material and into the ion-implanted well in exposed regions; and

performing at least one subsequent photolithography mask step comprises;

etching a pattern at the location of the alignment mark region but not in the cell area.

15. The method of claim 1 further comprising:

using a height difference at the alignment mark to determine where to form the cell pillars.

16. The method of claim 13 wherein:

forming cell stacking layers comprises forming the layers on top of the cell area and the area outside the cell area containing the alignment mark;

performing an alignment mark open step to remove cell stacking layers from the area outside the cell area containing the alignment mark region but not from the cell area.

17. The method of claim 12 wherein forming cell pillars comprises:

etching pillar holes in a column and row pattern such that the holes are formed through the cell stacking layers on regions between where the source lines were implanted.

18. The method of claim 17 further comprising:

depositing at least one gate dielectric layer;

performing another etch to extend each pillar hole through to the ion-implanted well over which the pillar hole exists;

forming a pillar body in each pillar hole, wherein each pillar body is formed in such a manner that during an erase operation of a flash memory produced using the method, the pillar body and the ion-implanted well form a single node.

19. The method of claim 17 wherein performing another etch to extend each pillar hole extends each pillar hole a defined distance into the ion-implanted well.

36. An apparatus that implements the method of claim 19.

20. A flash memory comprising:

a substrate;

a plurality of source lines formed in the substrate;

a plurality of cell stacking layers formed on the substrate containing the source lines;

a plurality of cell pillars in the cell stacking layers, each cell pillar having a pillar body, each pillar body being such that during an erase operation, the pillar body and the ion-implanted well form a single node;

a plurality of bitlines and a plurality of wordlines, the plurality of source lines being parallel to the plurality of bitlines and comprising a respective source line for each bitline.

21. The flash memory of claim 20 wherein the ion-implanted well is p-type silicon and the pillar bodies are p-type silicon.

22. The flash memory of claim 20 further comprising:

a plurality of trenches formed in the substrate and filled with a dielectric material;

wherein bitlines are parallel to the trenches, and each pillar body has an extension that passes through one of the trenches filled with dielectric material to the substrate.

23. The flash memory of claim 20 comprising a NAND flash memory device.

24. A method for making a flash memory device, comprising:

forming a cell substrate in a way that a silicon surface has regions with n-type and p-type silicon;

depositing cell stacking layers having gate material and interlayer dielectric; and

patterning word lines.

25. The method of claim 24, wherein the forming a cell substrate is conducted before the depositing a cell stack and the patterning word lines.

26. The method of claim 24 wherein the regions with n-type silicon in the cell substrate comprise n-type regions that are connected with each other in a way to form a line pattern which runs in a direction perpendicular to the word lines;

or

regions with p-type silicon in the cell substrate comprise p-type regions that are connected with each other in a way to form a line pattern which runs in a direction perpendicular to the word lines.

27. The method of claim 26 wherein:

the regions with n-type silicon are also connected in a direction parallel to the word lines;

or

wherein the regions with p-type silicon are also connected in a direction parallel to the word lines

28. The method of claim 24 further comprising:

forming cell pillars in the cell stacking layers that are aligned with the regions of p-type silicon;

or

forming cell pillars in the cell stacking layers that are aligned with the regions of n-type silicon.

29. The method of claim 28 further comprising:

after depositing the cell stacking layers, forming cell pillars at the regions of the p-type silicon;

or

after depositing the cell stacking layers, forming cell pillars at the regions of the n-type silicon.

30. The method of claim 29 further comprising:

manufacturing bodies of the cell pillars having p-type silicon, the bodies being connected to the underlying regions of p-type silicon without a junction in-between;

or

manufacturing bodies of the cell pillars having n-type silicon, the bodies being connected to the underlying regions of n-type silicon without a junction in-between.

31. The method of claim 24 wherein:

the regions of n-type silicon are also connected in a direction parallel to the word lines; and

p-type pillar bodies are connected to the p-type regions without a junction in between;

or

the regions of p-type silicon are also connected in a direction parallel to the word lines; and

n-type pillar bodies are connected to the n-type regions without a junction in between.

32. The method of claim 24 further comprising:

performing silicidation of the regions of n-type material to reduce resistance;

or

performing silicidation of the regions of p-type material to reduce resistance.

33. The method of claim 28 wherein the cell pillars comprise pillar bodies at least in part formed of undoped silicon.

34. The method of claim 24 wherein diffused source lines are formed at a same photolithography mask step used to define a location of an alignment mark without etching the silicon substrate in the cell area to form the source lines.

35. The method of claim 24 wherein source line locations are defined using etching as part of a photolithography mask step that is also used to define a location of an alignment mark.

41. A flash memory device manufactured by claim 24.

37. A device having a vertical structure of cells and diffused source lines running in a direction perpendicular to word lines, the device comprising cell pillars and a substrate having an ion-implanted well, wherein the cell pillars are formed so that during an erase operation, each cell pillar and the ion-implanted substrate form a single node.

38. A method comprising:

forming diffused source lines;

forming a cell stack;

performing patterning on the cell stack;

wherein forming diffused source lines is performed before proceeding with forming the cell stack and performing patterning.

39. A method comprising:

forming diffused source lines at a same photolithography mask step used to define a location of an alignment mark.

40. The method of claim 39 further comprising aligning cell locations to the alignment marks.