VERTICAL MEMORY CELL

• US 20140151776A1
• Filed: 11/26/2013
• Published: 06/05/2014
• Est. Priority Date: 07/27/2011
• Status: Abandoned Application

• Current Assignee: Micron Technology, Inc.
• Original Assignee: Micron Technology, Inc.
• Inventors: Beigel, Kurt D., Tang, Sanh D.
• Application Number:
  US14/090,689
• Publication Number:
  US 20140151776A1
• Time in Patent Office: Days
• US Class Current: 257/315
• CPC Class Codes: H01L 27/1027 Thyristors
• CPC Class Codes: H01L 29/0638 for preventing surface leakage due to surface inversion layer, e.g. with channel stopper channel stoppers in combination with isolation region for integrated circuits H01L21/762
• CPC Class Codes: H01L 29/0688 characterised by the particular shape of a junction between semiconductor regions
• CPC Class Codes: H01L 29/7841 with floating body, e.g. programmable transistors
• CPC Class Codes: H01L 29/78642 Vertical transistors
• CPC Class Codes: H01L 29/7889 Vertical transistors, i.e. transistors having source and drain not in the same horizontal plane
• CPC Class Codes: H10B 12/10 DRAM devices comprising bipolar components
• CPC Class Codes: H10B 12/20 DRAM devices comprising floating-body transistors, e.g. floating-body cells

Abstract

Methods of forming, devices, and apparatus associated with a vertical memory cell are provided. One example method of forming a vertical memory cell can include forming a semiconductor structure over a conductor line. The semiconductor structure can have a first region that includes a first junction between first and second doped materials. An etch-protective material is formed on a first pair of sidewalls of the semiconductor structure above the first region. A volume of the first region is reduced relative to a body region of the semiconductor structure in a first dimension.

Claims

1. A vertical memory cell, comprising:

a semiconductor material located between two electrodes, the semiconductor material having a plurality of doped regions and a junction between each pair of adjacent doped regions; and

a gate conductor formed adjacent one of the doped regions,

wherein a cross-sectional area of each junction is less than the cross-sectional area of the doped region having a gate conductor formed adjacent thereto.

2. The vertical memory cell of claim 1, wherein a cross-sectional area of a junction involving one side of the doped region having a gate conductor formed adjacent thereto is less than a cross-sectional area of a junction involving an opposite side of the doped region having a gate conductor formed adjacent thereto.

3. The vertical memory cell of claim 1, wherein a cross-sectional area of a junction involving a side of the doped region having a gate conductor formed adjacent thereto nearer a cathode is less than a cross-sectional area of a junction involving an opposite side of the doped region having a gate conductor formed adjacent thereto nearer an anode.

4. The vertical memory cell of claim 1, wherein one dimension of a junction cross-sectional area is reduced relative to a similar dimension of the cross-sectional area of the doped region having a gate conductor formed adjacent thereto.

5. The vertical memory cell of claim 1, wherein two dimensions of a junction cross-sectional area are reduced relative to similar dimensions of the cross-sectional area of the doped region having a gate conductor formed adjacent thereto.

6. The vertical memory cell of claim 5, wherein the cross-sectional area of the first junction is reduced in a second dimension by a reactive ion etch after the at least one gate structure is formed.

7. A vertical memory cell, comprising:

an N+ doped semiconductor cathode region formed on a cathode conductor;

a doped P-type semiconductor P-base region formed on the N+ doped semiconductor cathode region with a first junction therebetween;

an N-type semiconductor region formed on the doped P-type semiconductor P-base region with a second junction therebetween;

a P+ doped semiconductor anode region formed on the N-type semiconductor region with a third junction therebetween; and

at least one gate structure formed adjacent the doped P-type semiconductor P-base region, the at least one gate structure including conductive material offset from the doped P-type semiconductor P-base region by a gate dielectric,

wherein a cross-sectional area of at least one of the first, second, or third junctions is less than the cross-sectional area of the doped P-type semiconductor P-base region.

8. The vertical memory cell of claim 7, wherein the cross-sectional area of the first junction is less than the cross-sectional area of the doped P-type semiconductor P-base region.

9. The vertical memory cell of claim 8, wherein the cross-sectional area of the first junction is greater than the cross-sectional area of each of the second and third junctions.

10. The vertical memory cell of claim 7, wherein the cross-sectional area of the second junction is less than the cross-sectional area of the doped P-type semiconductor P-base region.

11. The vertical memory cell of claim 7, wherein the cross-sectional area of the third junction is less than the cross-sectional area of the doped P-type semiconductor P-base region.

12. The vertical memory cell of claim 11, wherein the cross-sectional area of the first junction is reduced in a first dimension by a reactive ion etch before the at least one gate structure is formed.

13. The vertical memory cell of claim 7, wherein the cross-sectional areas of each of the first, second, and third junctions are less than the cross-sectional area of the doped P-type semiconductor P-base region, and the cross-sectional area of each of the second and third junctions are less than the cross-sectional area of the first junction.

14. The vertical memory cell of claim 7, wherein the cross-sectional areas of each of the first, second, and third junctions are reduced in at least a first dimension by oxidizing respective semiconductors near the first, second, and third junctions.

15. A vertical memory cell, comprising:

a semiconductor structure formed over a conductor line, the semiconductor structure having a first region directly below a body region, the first region including a first junction between first and second doped materials; and

an etch-protective material formed on a first pair of sidewalls of the semiconductor structure above the first region; and

a gate structure formed adjacent the body region, and

wherein a cross-sectional area of the first region is smaller relative to a cross-sectional area of the body region in a first dimension.

16. The vertical memory cell of claim 15, wherein the cross-sectional area of the first region is smaller than the cross-sectional area of the body region in a second dimension, the second dimension being orthogonal to the first dimension.

17. The vertical memory cell of claim 16, wherein the semiconductor structure includes a second junction between second and third doped materials in a second region above the body region, and wherein a cross-sectional area of the second region is smaller than the cross-sectional area of the body region in the first dimension.

18. The vertical memory cell of claim 17, wherein the cross-sectional area of the second region is smaller than the cross-sectional area of the first region in the first dimension.

19. The vertical memory cell of claim 17, wherein a cross-sectional area of the second region is smaller than the cross-sectional area of the body region in the second dimension.

20. The vertical memory cell of claim 17, wherein the third doped material is formed above the second doped material in the second region, and the semiconductor structure includes a fourth doped material formed above the third doped material in the second region, and wherein the first doped material is an N+ doped material, the second doped material is a doped P-base material, the third doped material is an N-base material, and the fourth doped material is a P+ doped material.