Semiconductor Device Including Trenches and Method of Manufacturing a Semiconductor Device

• US 20140151789A1
• Filed: 11/30/2012
• Published: 06/05/2014
• Est. Priority Date: 11/30/2012
• Status: Active Grant

• Current Assignee: Infineon Technologies AG
• Original Assignee: Infineon Technologies AG
• Inventors: Cotorogea, Maria, Felsl, Hans Peter, Santos Rodriguez, Francisco Javier, Schulze, Hans-Joachim, Gawlina, Yvonne, Seibert, Georg, Stegner, Andre Rainer, Wagner, Wolfgang
• Granted Patent: US 8,853,774 B2
• Time in Patent Office: Days
• US Class Current: 257/334
• CPC Class Codes: H01L 21/823481 isolation region manufacturing related aspects, e.g. to avoid interaction of isolation region with adjacent structure
• CPC Class Codes: H01L 27/088 the components being field-effect transistors with insulated gate
• CPC Class Codes: H01L 29/0623 Buried supplementary region, e.g. buried guard ring multi-RESURF H01L29/0634
• CPC Class Codes: H01L 29/0653 adjoining the input or output region of a field-effect device, e.g. the source or drain region
• CPC Class Codes: H01L 29/0696 of cellular field-effect devices, e.g. multicellular DMOS transistors or IGBTs
• CPC Class Codes: H01L 29/0878 Impurity concentration or distribution
• CPC Class Codes: H01L 29/407 Recessed field plates, e.g. trench field plates, buried field plates
• CPC Class Codes: H01L 29/42368 the thickness being non-uniform
• CPC Class Codes: H01L 29/66734 with a step of recessing the gate electrode, e.g. to form a trench gate electrode
• CPC Class Codes: H01L 29/7813 with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236

Abstract

A semiconductor device includes a first transistor cell including a first gate electrode in a first trench. The semiconductor device further includes a second transistor cell including a second gate electrode in a second trench, wherein the first and second gate electrodes are electrically connected. The semiconductor device further includes a third trench between the first and second trenches, wherein the third trench extends deeper into a semiconductor body from a first side of the semiconductor body than the first and second trenches. The semiconductor device further includes a dielectric in the third trench covering a bottom side and walls of the third trench.

Claims

1. A semiconductor device, comprising:

a first transistor cell including a first gate electrode in a first trench;

a second transistor cell including a second gate electrode in a second trench, wherein the first and second gate electrodes are electrically connected;

a third trench between the first and second trenches, wherein the third trench extends deeper into a semiconductor body from a first side of the semiconductor body than the first and second trenches; and

a dielectric in the third trench covering a bottom side and walls of the third trench,

wherein a thickness of the dielectric lining a wall of the third trench at a vertical level coinciding with a gate dielectric in the first and second trenches is greater than a thickness of the gate dielectric in the first and second trenches.

2. The semiconductor device of claim 1, wherein the third trench is wider at the first side than the first and second trenches.

3. The semiconductor device of claim 1, wherein a depth of the first and second trenches equals d₁.

4. The semiconductor device of claim 1, wherein the third trench further includes a conductive material.

5. The semiconductor device of claim 4, wherein the conductive material is electrically floating.

6. The semiconductor device of claim 4, wherein the conductive material is electrically connected to the first and second gate electrodes.

7. The semiconductor device of claim 4, wherein each one of the first and second transistor cells includes a source electrode, and wherein the conductive material of the third trench is electrically connected to the source electrode of the first and second transistor cells.

8. The semiconductor device of claim 1, wherein the semiconductor body includes a drift zone of a first conductivity type adjoining a bottom side of a body region of a second conductivity type complementary to the first conductivity type;

and wherein a first semiconductor region of the first conductivity type including a net doping concentration higher than the drift zone adjoins a bottom side of the third trench.

9. The semiconductor device of claim 1, wherein the semiconductor body includes a drift zone of a first conductivity type adjoining a bottom side of a body region of a second conductivity type complementary to the first conductivity type;

and wherein a second semiconductor region of the second conductivity type including a net doping concentration higher than the drift zone adjoins a bottom side of the first and second trenches.

10. The semiconductor device of claim 1, wherein the semiconductor body includes a drift zone of a first conductivity type adjoining a bottom side of a body region of a second conductivity type complementary to the first conductivity type;

and wherein a first semiconductor region including a net doping concentration higher than the drift zone adjoins a bottom side of the third trench; and

a second semiconductor region of a conductivity type opposite to the first semiconductor region and including a net doping concentration higher than the drift zone adjoins a bottom side of the first and second trenches.

11. The semiconductor device of claim 1, wherein each one of the first and second trenches has a depth d₁ and a width w₁, and wherein a depth d₃ of the third trench ranges between d₁+0.5 μ

m and d₁+4 μ

m.

12. The semiconductor device of claim 11, wherein d₁ ranges between 1 μ

m and 8 μ

m.

13. The semiconductor device of claim 1, wherein each one of the first and second trenches has a width w₁, the third trench has a width w₃, and w₁ ranges between 0.05×

w₃ and w₃.

14. The semiconductor device of claim 1, further comprising a fourth trench between transistor cells of the semiconductor device, wherein a depth d₄ of the fourth trench is greater than a depth d₁ of the first and second trenches, and the depth d₄ differs from a depth d₃ of the third trench.

15. The semiconductor device of claim 1, wherein source regions adjoin only the first and second trenches with respect to the first to third trenches.

17. The semiconductor device of claim 1, wherein the third trench is contiguous and surrounds the first transistor cell.

18. The semiconductor device of claim 1, wherein the third trench includes a plurality of trench segments surrounding the first transistor cell.

19. The semiconductor device of claim 1, wherein each one of the first and second trenches is shaped as one of a stripe and a polygon.

20. An integrated circuit including the semiconductor device of claim 1.

16. (canceled)

21. A method of manufacturing a semiconductor device, comprising:

forming a first transistor cell including a first gate electrode in a first trench;

forming a second transistor cell including a second gate electrode in a second trench, wherein the first and second gate electrodes are electrically connected;

forming a third trench between the first and second trenches, wherein the third trench extends deeper into a semiconductor body from a first side of the semiconductor body than the first and second trenches; and

forming a dielectric in the third trench covering a bottom side and sidewalls of the third trench,

wherein forming the first, second and third trenches includes forming a patterned mask at the first side, wherein the patterned mask includes a first type of opening having a greater lateral width than a second type of opening, and etching the first and second trenches through the second type of opening and the third trench through the first type of opening.

23. The method of claim 21, further comprising filling up the third trench with at least one dielectric material.

24. The method of claim 21, further comprising introducing dopants through a bottom side of the third trench into the semiconductor body before filling up the third trench.

25. The method of claim 21, further comprising introducing dopants through a bottom side of the first and second trenches into the semiconductor body before filling up the first and second trenches.

22. (canceled)

26. A method of manufacturing a semiconductor device, comprising:

forming a first transistor cell including a first gate electrode in a first trench;

forming a second transistor cell including a second gate electrode in a second trench, wherein the first and second gate electrodes are electrically connected;

forming a third trench between the first and second trenches, wherein the third trench extends deeper into a semiconductor body from a first side of the semiconductor body than the first and second trenches;

forming a dielectric in the third trench covering a bottom side and sidewalls of the third trench; and

introducing dopants through a bottom side of the third trench into the semiconductor body before filling up the third trench.

27. A semiconductor device, comprising:

a first transistor cell including a first gate electrode in a first trench;

a second transistor cell including a second gate electrode in a second trench, wherein the first and second gate electrodes are electrically connected;

a third trench between the first and second trenches, wherein the third trench extends deeper into a semiconductor body from a first side of the semiconductor body than the first and second trenches; and

a dielectric in the third trench covering a bottom side and walls of the third trench,

wherein the semiconductor body includes a drift zone of a first conductivity type adjoining a bottom side of a body region of a second conductivity type complementary to the first conductivity type,

wherein a second semiconductor region of the second conductivity type including a net doping concentration higher than the drift zone adjoins a bottom side of the first and second trenches.