METHOD OF OPERATING WRITE ASSIST CIRCUITRY
First Claim
Patent Images
1. A method comprising:
- generating a first pull up current at a first node in a word line driver circuit; and
generating a second pull up current at a second node in a tracking word line driver circuit,whereinthe second pull up current is higher than the first pull up current;
when the first node is at a first node high logic level, a word line generated by the word line driver circuit is at a word line low logic level, and when the first node is at a first node low logic level, the word line is at a word line high logic level; and
when the second node is at a second node high logic level, a tracking word line generated by the tracking word line driver is at a tracking word line low logic level, and when the second node is at a second node low logic level, the tracking word line is at a tracking word line high logic level.
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Abstract
A method includes causing, by a first circuit, a first signal transition at a first node based on a clock signal. A first edge, from a first level to a second level, of a word line signal is generated responsive to the first signal transition. A second signal transition at a second node is caused by a second circuit based on the clock signal. The second circuit and the first circuit are configured to cause the second signal transition to occur later than the first signal transition by a delay time. A first edge, from a third logic level to a fourth level, of a tracking word line signal is generated responsive to the second signal transition.
133 Citations
20 Claims
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1. A method comprising:
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generating a first pull up current at a first node in a word line driver circuit; and generating a second pull up current at a second node in a tracking word line driver circuit, wherein the second pull up current is higher than the first pull up current; when the first node is at a first node high logic level, a word line generated by the word line driver circuit is at a word line low logic level, and when the first node is at a first node low logic level, the word line is at a word line high logic level; and when the second node is at a second node high logic level, a tracking word line generated by the tracking word line driver is at a tracking word line low logic level, and when the second node is at a second node low logic level, the tracking word line is at a tracking word line high logic level. - View Dependent Claims (2, 3, 4, 5, 6)
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7. A method comprising:
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causing, by a first circuit, a transition at a first node from a first node high logic level to a first node low logic level, thereby generating a transition of a word line signal from a word line low logic level to a word line high logic level; causing, by a second circuit, a transition at a second node from a second node high logic level to a second node low logic level, thereby generating a transition of a tracking word line signal from a tracking word line low logic level to a tracking word line high logic level; generating a further transition of the word line signal from the word line high logic level to the word line low logic level, thereby generating a word line pulse width; and generating a further transition of the tracking word line signal from the tracking word line high logic level to the tracking word line low logic level, thereby generating a tracking word line pulse width, wherein the second circuit is configured to have pull-up driving capability greater than that of the first circuit; the transition of the tracking word line signal from the tracking word line low logic level to the tracking word line high logic level is later than the transition of the word line signal from the word line low logic level to the word line high logic level by a delay time; and the word line pulse width is larger than the tracking word line pulse width. - View Dependent Claims (8, 9, 10, 11, 12, 13)
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14. A method comprising:
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causing, by a first circuit, a first signal transition at a first node based on a clock signal; generating a first edge, from a first level to a second level, of a word line signal responsive to the first signal transition; causing, by a second circuit, a second signal transition at a second node based on the clock signal, the second circuit and the first circuit being configured to cause the second signal transition to occur later than the first signal transition by a delay time; and generating a first edge, from a third logic level to a fourth level, of a tracking word line signal responsive to the second signal transition. - View Dependent Claims (15, 16, 17, 18, 19, 20)
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Specification