METHOD, COMPUTER PROGRAM PRODUCT, AND SYSTEM FOR MULTI-THREADED VIDEO ENCODING

• US 20140153635A1
• Filed: 12/05/2012
• Published: 06/05/2014
• Est. Priority Date: 12/05/2012
• Status: Abandoned Application

• Current Assignee: NVIDIA Corporation
• Original Assignee: NVIDIA Corporation
• Inventors: Shi, Haixia, Lapicque, Olivier, Yang, Xiaohua, Zhang, Guanjun
• Application Number:
  US13/706,302
• Publication Number:
  US 20140153635A1
• Time in Patent Office: Days
• US Class Current: 375/240.02
• CPC Class Codes: H04N 19/423 characterised by memory arrangements H04N19/433 takes precedence
• CPC Class Codes: H04N 19/436 using parallelised computational arrangements

Abstract

A method, computer program product, and system are provided for multi-threaded video encoding. The method includes the steps of generating a set of motion vectors in a hardware video encoder based on a current frame of a video stream and a reference frame of the video stream, dividing the current frame into a number of slices, encoding each slice of the current frame based on the set of motion vectors, and combining the encoded slices to generate an encoded bitstream.

Claims

1. A method comprising:

generating a set of motion vectors in a hardware video encoder based on a current frame of a video stream and a reference frame of the video stream;

dividing the current frame into a number of slices;

encoding each slice of the current frame based on the set of motion vectors; and

combining the encoded slices to generate an encoded bitstream.

2. The method of claim 1, wherein the encoded bitstream is a VC-1 compatible bitstream.

3. The method of claim 1, further comprising:

generating a master thread configured to combine the encoded slices; and

generating two or more child threads, wherein each child thread is configured to encode a particular slice of the current frame allocated to the child thread.

4. The method of claim 3, wherein the master thread and the two or more child threads are configured to be executed in a parallel processing unit.

5. The method of claim 4, wherein the hardware video encoder and the parallel processing unit are included in a system-on-chip (SoC).

6. The method of claim 3, wherein each child thread of the two or more child threads is configured to generate a byte-aligned encoded slice by encoding motion vectors and quantized transform coefficients using variable length codes to generate a portion of the encoded bitstream.

7. The method of claim 6, wherein each child thread of the two or more child threads is configured to add one or more stuffing bits to the portion of the encoded bitstream generated by that child thread such that the portion is byte-aligned.

8. The method of claim 1, further comprising transmitting a copy of the current frame to the hardware video encoder.

9. The method of claim 8, wherein a driver receives instructions from an application and is configured to transmit the copy of the current frame to the hardware video encoder.

10. The method of claim 9, wherein the hardware video encoder notifies the driver that the set of motion vectors is available, and wherein the driver is configured to generate one or more threads for execution by a parallel processing unit to encode each slice of the current frame based on the set of motion vectors and combine the encoded slices to generate the encoded bitstream.

11. The method of claim 1, wherein the hardware video encoder is configured to implement an H.264/MPEG Part 10 (Advanced Video Coding) standard for video compression.

12. The method of claim 11, wherein the hardware video encoder includes a motion estimation engine that is configured to generate the set of motion vectors.

13. The method of claim 1, wherein the hardware video encoder is configured to implement an MPEG-2 standard for video compression.

14. A non-transitory computer-readable storage medium storing instructions that, when executed by a processor, cause the processor to perform steps comprising:

generating a set of motion vectors in a hardware video encoder based on a current frame of a video stream and a reference frame of the video stream;

dividing the current frame into a number of slices;

encoding each slice of the current frame based on the set of motion vectors; and

combining the encoded slices to generate an encoded bitstream

15. The non-transitory computer-readable storage medium of claim 14, wherein the encoded bitstream is a VC-1 compatible bitstream.

16. The non-transitory computer-readable storage medium of claim 14, the steps further comprising:

generating a master thread configured to combine the encoded slices; and

generating two or more child threads, wherein each child thread is configured to encode a particular slice of the current frame allocated to the child thread.

17. A system comprising:

a hardware video encoder configured to generate a set of motion vectors based on a current frame of a video stream and a reference frame of the video stream; and

a processor coupled to the hardware video encoder and configured to;

divide the current frame into a number of slices,

encode each slice of the current frame based on the set of motion vectors, and

combine the encoded slices to generate an encoded bitstream.

18. The system of claim 17, wherein the encoded bitstream is a VC-1 compatible bitstream.

19. The system of claim 17, wherein the hardware video encoder is configured to implement an H.264/MPEG Part 10 (Advanced Video Coding) standard for video compression

20. The system of claim 17, wherein the processor is a graphics processing unit, and wherein the processor is further configured to execute a master thread configured to combine the encoded slices and two or more child threads, wherein each child thread is configured to encode a particular slice of the current frame allocated to the child thread.