METHOD FOR MANUFACTURING N-TYPE MOSFET

• US 20140154853A1
• Filed: 12/07/2012
• Published: 06/05/2014
• Est. Priority Date: 11/30/2012
• Status: Active Grant

• Current Assignee: Institute of Microelectronics Chinese Academy of Sciences (Chinese Academy of Sciences)
• Original Assignee: Institute of Microelectronics Chinese Academy of Sciences (Chinese Academy of Sciences)
• Inventors: Xu, Qiuxia, Zhu, Huilong, Zhou, Huajie, Xu, Gaobo
• Granted Patent: US 9,029,225 B2
• Time in Patent Office: Days
• US Class Current: 438/290
• CPC Class Codes: H01L 21/28088 the final conductor layer next to the insulator being a composite, e.g. TiN
• CPC Class Codes: H01L 21/28176 with a treatment, e.g. annealing, after the formation of the definitive gate conductor
• CPC Class Codes: H01L 29/4966 the conductor material next to the insulator being a composite material, e.g. organic material, TiN, MoSi2 H01L29/4908, H01L29/4983 take precedence
• CPC Class Codes: H01L 29/513 the variation being perpendicular to the channel plane
• CPC Class Codes: H01L 29/517 the insulating material comprising a metallic compound, e.g. metal oxide, metal silicate H01L29/518 takes precedence
• CPC Class Codes: H01L 29/518 the insulating material containing nitrogen, e.g. nitride, oxynitride, nitrogen-doped material
• CPC Class Codes: H01L 29/66545 using a dummy, i.e. replacement gate in a process wherein at least a part of the final gate is self aligned to the dummy gate

Abstract

The present disclosure discloses a method for manufacturing an N-type MOSFET, comprising: forming a part of the MOSFET on a semiconductor substrate, the part of the MOSFET comprising source/drain regions in the semiconductor substrate, a replacement gate stack between the source/drain regions above the semiconductor substrate, and a gate spacer surrounding the replacement gate stack; removing the replacement gate stack of the MOSFET to form a gate opening exposing a surface of the semiconductor substrate; forming an interface oxide layer on the exposed surface of the semiconductor; forming a high-K gate dielectric layer on the interface oxide layer in the gate opening; forming a first metal gate layer on the high-K gate dielectric layer; implanting dopant ions into the first metal gate layer; and performing annealing to cause the dopant ions to diffuse and accumulate at an upper interface between the high-K gate dielectric layer and the first metal gate layer and a lower interface between the high-K gate dielectric layer and the interface oxide layer, and also to generate electric dipoles by interfacial reaction at the lower interface between the high-K gate dielectric layer and the interface oxide layer.

Claims

1. A method for manufacturing an N-type MOSFET, comprising:

forming a part of the MOSFET on a semiconductor substrate, the part of the MOSFET comprising source/drain regions in the semiconductor substrate, a replacement gate stack between the source/drain regions above the semiconductor substrate, and a gate spacer surrounding the replacement gate stack;

removing the replacement gate stack of the MOSFET to form a gate opening exposing a surface of the semiconductor substrate;

forming an interface oxide layer on the exposed surface of the semiconductor;

forming a high-K gate dielectric layer on the interface oxide layer in the gate opening;

forming a first metal gate layer on the high-K gate dielectric layer;

implanting dopant ions into the first metal gate layer;

forming a second metal gate layer on the first metal gate layer to fill the gate opening; and

performing annealing to cause the dopant ions to diffuse and accumulate at an upper interface between the high-K gate dielectric layer and the first metal gate layer and a lower interface between the high-K gate dielectric layer and the interface oxide layer, and also to generate electric dipoles by interfacial reaction at the lower interface between the high-K gate dielectric layer and the interface oxide layer.

2. The method according to claim 1, wherein the high-K gate dielectric layer comprise any one selected from ZrO₂, ZrON, ZrSiON, HfZrO, HfZrON, HfON, HfO₂, HfAlO, HfAlON, HfSiO, HfSiON, HfLaO, HfLaON, and any combination thereof.

3. The method according to claim 1, wherein the high-K gate dielectric layer has a thickness of about 1.5-5 nm.

4. The method according to claim 1, wherein the high-K gate dielectric layer is formed by any one of atom layer deposition, physical vapor deposition, and metal organic chemical vapor deposition.

5. The method according to claim 4, further comprising performing additional annealing after forming the high-K gate dielectric layer to improve quality of the high-K gate dielectric layer.

6. The method according to claim 1, wherein the first metal gate layer comprises any one selected from TiN, TaN, MoN, WN, TaC, TaCN, and any combination thereof.

7. The method according to claim 1, wherein the first metal gate layer has a thickness of about 2-10 nm.

8. The method according to claim 1, wherein the second metal gate layer comprises any one selected from W, Ti, TiAl, Al, Mo, Ta, TiN, TaN, WN, and any combination thereof.

9. The method according to claim 1, wherein in implanting the dopant ions into the first metal gate layer, energy and dosage of ion implantation is controlled according to a desired threshold voltage to cause the dopant ions to distribute only in the first metal gate layer.

10. The method according to claim 9, wherein the energy of the ion implantation is about 0.2 KeV-30 KeV.

11. The method according to claim 9, wherein the dosage of the ion implantation is about 1E13-1E15 cm⁻

2.

12. The method according to claim 1, wherein dopant ions implanted into the first metal gate layer is capable of reducing effective work function.

13. The method according to claim 12, wherein the dopant is any one selected from P, As, Sb, La, Er, Dy, Gd, Sc, Yb, Er, and Tb.

14. The method according to claim 1, wherein the annealing is performed in inert gas environment or weak reduction gas environment at about 350°

C.-450°

C. for about 20-90 minutes.