ROW HAMMER MONITORING BASED ON STORED ROW HAMMER THRESHOLD VALUE

• US 20140156923A1
• Filed: 11/30/2012
• Published: 06/05/2014
• Est. Priority Date: 11/30/2012
• Status: Active Grant

• Current Assignee: Intel Corporation
• Original Assignee: Intel Corporation
• Inventors: Bains, Kuljit S., Halbert, John B.
• Granted Patent: US 9,032,141 B2
• Time in Patent Office: Days
• US Class Current: 711/106
• CPC Class Codes: G06F 13/1636 using refresh
• CPC Class Codes: G11C 11/40611 External triggering or timing of internal or partially internal refresh operations, e.g. auto-refresh or CAS-before-RAS triggered refresh
• CPC Class Codes: G11C 11/4078 Safety or protection circuits, e.g. for preventing inadvertent or unauthorised reading or writing; Status cells; Test cells protection of memory contents during checking or testing G11C29/52
• CPC Class Codes: G11C 11/408 Address circuits
• CPC Class Codes: G11C 29/50 Marginal testing, e.g. race, voltage or current testing
• CPC Class Codes: G11C 29/50012 of timing
• CPC Class Codes: G11C 7/24 Memory cell safety or protection circuits, e.g. arrangements for preventing inadvertent reading or writing; Status cells; Test cells

Abstract

Detection logic of a memory subsystem obtains a threshold for a memory device that indicates a number of accesses within a time window that causes risk of data corruption on a physically adjacent row. The detection logic obtains the threshold from a register that stores configuration information for the memory device, and can be a register on the memory device itself and/or can be an entry of a configuration storage device of a memory module to which the memory device belongs. The detection logic determines whether a number of accesses to a row of the memory device exceeds the threshold. In response to detecting the number of accesses exceeds the threshold, the detection logic can generate a trigger to cause the memory device to perform a refresh targeted to a physically adjacent victim row.

Claims

1. A memory subsystem comprising:

a memory device having multiple physical rows of memory cells; and

detection logic coupled to the memory device, the detection logic to

obtain an access rate threshold for the memory device from a register that stores configuration information for the memory device, the threshold identifying a number of accesses to a specific row of memory within a time window that causes risk of data corruption on a row physically adjacent to the accessed row;

determine based on the threshold whether a number of accesses to one of the multiple physical rows of the memory device exceeds the threshold; and

in response to detecting that the number of accesses exceeds the threshold, trigger the memory device to perform a refresh targeted to a victim row physically adjacent to the row for which the number of accesses exceeded the threshold.

2. The memory subsystem of claim 1, wherein the detection logic comprises detection logic of a memory controller coupled to the memory device.

3. The memory subsystem of claim 1, wherein the detection logic comprises distributed detection logic of the memory device.

4. The memory subsystem of claim 1, wherein the register that stores configuration information for the memory device comprises a configuration storage device of a memory module of which the memory device is a part.

5. The memory subsystem of claim 1, wherein the register that stores configuration information for the memory device comprises a configuration register on the memory device.

6. The memory subsystem of claim 1, wherein the detection logic is to obtain a three-bit code that indicates the threshold.

7. The memory subsystem of claim 1, wherein the threshold for the memory device is a first threshold, and is different from a second threshold for a different memory device in the memory subsystem.

8. The memory subsystem of claim 7, wherein the detection logic monitors each memory device in accordance with its different threshold.

9. The memory subsystem of claim 7, wherein the detection logic is to further

determine which threshold is lower;

and

monitor the memory devices in accordance with the lower threshold.

10. An electronic device comprising:

a memory subsystem having

a memory device having multiple physical rows of memory cells; and

detection logic coupled to the memory device, the detection logic to

obtain an access rate threshold for the memory device from a register that stores configuration information for the memory device, the threshold identifying a number of accesses to a specific row of memory within a time window that causes risk of data corruption on a row physically adjacent to the accessed row;

determine based on the threshold whether a number of accesses to one of the multiple physical rows of the memory device exceeds the threshold; and

in response to detecting that the number of accesses exceeds the threshold, trigger the memory device to perform a refresh targeted to a victim row physically adjacent to the row for which the number of accesses exceeded the threshold; and

a touchscreen display device configured to provide a user display based on data accessed from the memory device.

11. The electronic device of claim 10, wherein the register that stores configuration information for the memory device comprises a configuration storage device of a memory module of which the memory device is a part.

12. The electronic device of claim 10, wherein the register that stores configuration information for the memory device comprises a configuration register on the memory device.

13. The electronic device of claim 10, wherein the threshold for the memory device is a first threshold, and is different from a second threshold for a different memory device in the memory subsystem.

14. The electronic device of claim 13, wherein the detection logic monitors each memory device in accordance with its different threshold.

15. The electronic device of claim 13, wherein the detection logic is to further

determine which threshold is lower;

and

monitor the memory devices in accordance with the lower threshold.

16. The electronic device of claim 10, wherein the detection logic is to obtain a field of a configuration register that stores a code indicating the threshold.

17. A method comprising:

obtaining an access rate threshold for a memory device from a register that stores configuration information for the memory device, the threshold identifying a number of accesses to a specific row of memory within a time window that causes risk of data corruption on a row physically adjacent to the accessed row;

determining based on the threshold whether a number of accesses to one of the multiple physical rows of the memory device exceeds the threshold; and

in response to detecting that the number of accesses exceeds the threshold, generating a trigger to cause the memory device to perform a refresh targeted to a victim row physically adjacent to the row for which the number of accesses exceeded the threshold.

18. The method of claim 17, wherein generating the trigger comprises sending an alert from distributed detection logic at the memory device to a memory controller to cause the memory controller to issue a targeted refresh command to the memory device.

19. The method of claim 17, wherein determining whether the number of access exceeds the threshold further comprises:

monitoring accesses to rows of the memory device for the time window;

determining if a number of accesses for any of the rows exceeds the threshold; and

indicating address information for a row determined to exceed the number of accesses in the time window.

20. The method of claim 17, wherein the threshold for the memory device is a first threshold, different from a second threshold for a different memory device sharing a memory subsystem with the memory device, and wherein determining based on the threshold further comprises:

determining whether the first or second threshold is lower; and

monitoring both memory devices based on the determined lower threshold.