NETWORK-ON-CHIP USING REQUEST AND REPLY TREES FOR LOW-LATENCY PROCESSOR-MEMORY COMMUNICATION

• US 20140156929A1
• Filed: 12/04/2012
• Published: 06/05/2014
• Est. Priority Date: 12/04/2012
• Status: Active Grant

• Current Assignee: Ecole polytechnique fãdãrale de lausanne epfl (Schweizerische Eidgenossenschaft)
• Original Assignee: Ecole polytechnique fãdãrale de lausanne epfl (Schweizerische Eidgenossenschaft)
• Inventors: FALSAFI, Babak, GROT, Boris, LOTFI KAMRAN, Pejman
• Granted Patent: US 9,703,707 B2
• Time in Patent Office: Days
• US Class Current: 711/122
• CPC Class Codes: G06F 12/0811 with multilevel cache hierarchies
• CPC Class Codes: G06F 12/0813 with a network or matrix configuration
• CPC Class Codes: G06F 15/7825 Globally asynchronous, locally synchronous, e.g. network on chip

Abstract

A Network-On-Chip (NOC) organization comprises a die having a cache area and a core area, a plurality of core tiles arranged in the core area in a plurality of subsets, at least one cache memory bank arranged in the cache area, whereby the at least one cache memory bank is distinct from each of the plurality of core tiles. The NOC organization further comprises an interconnect fabric comprising a request tree to connect to a first cache memory bank of the at least one cache memory bank, each core tile of a first one of the subsets, the first subset corresponding to the first cache memory bank, such that each core tile of the first subset is connected to the first cache memory bank only, and allow guiding data packets from each core tile of the first subset to the first memory bank, and a reply tree to connect the first cache memory bank to each core tile of the first subset, and allow guiding data packets from the first cache memory bank to a core tile of the first subset.

Claims

1. A Network-On-Chip (NOC) organization comprising

a die having a cache area and a core area,

a plurality of core tiles arranged in the core area in a plurality of subsets,

at least one cache memory bank arranged in the cache area,

whereby the at least one cache memory bank is distinct from each of the plurality of core tiles,

an interconnect fabric comprising

a request tree to connect to a first cache memory bank of the at least one cache memory bank, each core tile of a first one of the subsets, the first subset corresponding to the first cache memory bank, such that each core tile of the first subset is connected to the first cache memory bank only, and allow guiding data packets from each core tile of the first subset to the first memory bank, and

a reply tree to connect the first cache memory bank to each core tile of the first subset, and allow guiding data packets from the first cache memory bank to a core tile of the first subset.

2. The NOC organization of claim 1, wherein each subset of core tiles corresponds to only one cache memory bank.

3. The NOC organization of claim 1, wherein in case two or more cache memory banks are present, and the cache memory banks are connected among themselves

4. The NOC organization of claim 3, wherein the cache memory banks are connected by means of a flattened butterfly network architecture.

5. The NOC organization of claim 1, wherein the request tree comprises a plurality of request nodes, each one of which is a two-input multiplexer that merges data packets from the first input and the second input and outputs a multiplexed stream of data packets.

6. The NOC organization of claim 5, wherein

at a first request node, a first two-input multiplexer comprises

means to receive

first data packets from a first core tile at its first input,

a first multiplexed stream of data packets at its second input, from a second two-input multiplexer located at a second request node, and

means to output

a resulting stream of data packets to the first cache memory bank, at the second request node, the second two-input multiplexer comprises means to receive

second data packets from a second tile at its first input,

a second multiplexed stream of data packets at its second input, from a third two-input multiplexer located at a third request node, or

third data packets from a third core tile at its second input, depending on the case if the first subset comprises more than three core tiles or not, and

means to output

the first multiplexed stream of data packets.

7. The NOC organization of claim 5, wherein each two-input multiplexer comprises means to implement a static-priority arbitration policy that prioritizes the output of the data packets received at the first input over the data packets received at the second input.

8. The NOC organization of claim 1, wherein the reply tree comprises a plurality of reply nodes, each one of which is a single input demultiplexer that demultiplexes an input multiplexed stream of data packets and propagates a data packet therefrom to a first output connected to one of the core tiles of the first subset if the packet has reached its destination or propagates it to a second output otherwise.

9. The NOC organization of claim 8, further comprising

at a first reply node, a first single input demultiplexer which comprises

means to receive

a first reply multiplexed stream of data packets from the first cache memory bank, and

means to determine whether a packet in the first reply multiplexed stream has reached its destination at the first reply node, whereby the destination corresponds to the core tile connected to the first output,

means to output the packet to the first output if the packet has reached its destination,

means to multiplex the remaining packets in a second reply multiplexed stream, and

means to output the second reply multiplexed stream to the second output,

at a second reply node, a second single input demultiplexer, which is configured in a similar manner as the first single input demultiplexer notably with respect to a further core tile connected to its first output, and either a third single input demultiplexer or an even further core tile connected to its second output depending on the case if the first subset comprises more than three core tiles or not.

10. The NOC organization of claim 8, wherein each single input multiplexer comprises means to implement a static-priority reply arbitration policy that prioritizes the output of the data packets received at the single input.

11. The NOC organization of claim 1, wherein the cache area divides a total area of the die in two substantially equally sized areas, and the core area is located in the two substantially equally sized areas hence surrounding the cache area.

12. The NOC organization of claim 11, wherein the cache area has a rectangular shape in which the at least one cache memory banks are aligned according to the elongated direction of the rectangular shape, and for each subset, the core tiles making up the subset at aligned along a direction perpendicular to the elongated direction of the rectangular shape.

13. The NOC organization of claim 1, wherein the cache area corresponds to central area located substantially in the geometrical middle of the die.