Control Transfer Termination Instructions Of An Instruction Set Architecture (ISA)

• US 20140156972A1
• Filed: 11/30/2012
• Published: 06/05/2014
• Est. Priority Date: 11/30/2012
• Status: Active Grant

• Current Assignee: Intel Corporation
• Original Assignee: Intel Corporation
• Inventors: Shanbhogue, Vedyvas, Brandt, Jason W., Savagaonkar, Uday R., Sahita, Ravi L.
• Granted Patent: US 9,703,567 B2
• Time in Patent Office: Days
• US Class Current: 712/205
• CPC Class Codes: G06F 21/52 during program execution, e.g. stack integrity ; Preventing unwanted data erasure; Buffer overflow
• CPC Class Codes: G06F 21/71 to assure secure computing or processing of information
• CPC Class Codes: G06F 9/3005 to perform operations for flow control
• CPC Class Codes: G06F 9/30054 Unconditional branch instructions
• CPC Class Codes: G06F 9/30076 to perform miscellaneous control operations, e.g. NOP
• CPC Class Codes: G06F 9/3012 Organisation of register space, e.g. banked or distributed register file
• CPC Class Codes: G06F 9/30145 Instruction analysis, e.g. decoding, instruction word fields
• CPC Class Codes: G06F 9/3851 from multiple instruction streams, e.g. multistreaming
• CPC Class Codes: G06F 9/3858 Result writeback, i.e. updating the architectural state or memory
• CPC Class Codes: G06F 9/3861 Recovery, e.g. branch miss-prediction, exception handling error detection or correction G06F11/00

Abstract

In an embodiment, the present invention includes a processor having an execution logic to execute instructions and a control transfer termination (CTT) logic coupled to the execution logic. This logic is to cause a CTT fault to be raised if a target instruction of a control transfer instruction is not a CTT instruction. Other embodiments are described and claimed.

Claims

1. A processor comprising:

a fetch unit to fetch instructions;

a decode unit to decode the instructions, the decode unit including a control transfer termination (CTT) logic, responsive to a control transfer instruction, to decode the control transfer instruction into a decoded control transfer instruction;

an execution unit to execute decoded instructions; and

a retirement unit to retire the decoded control transfer instruction, wherein the retirement unit is to raise a fault if a next instruction to be retired after the decoded control transfer instruction is not a CTT instruction.

2. The processor of claim 1, wherein the decode unit is to associate a second state with the decoded control transfer instruction to indicate that the CTT logic is in a wait state.

3. The processor of claim 2, wherein the decode unit is to associate a first state with a decoded CTT instruction decoded by the decode unit after the control transfer instruction, to indicate that the CTT logic is in an idle state.

4. The processor of claim 3, wherein the decode unit is to provide the decoded control transfer instruction and the second state to the execution unit.

5. The processor of claim 4, wherein the retirement unit is to communicate a last retired instruction and a state of the CTT logic associated with the last retired instruction to the decode unit responsive to a misprediction, wherein the decode unit is to update a state of the CTT logic using the communicated state.

6. The processor of claim 3, wherein the CTT logic is to insert a fault instruction when an instruction decoded after the control transfer instruction is not a CTT instruction.

7. The processor of claim 6, wherein the retirement unit is to raise the fault responsive to the fault instruction, the fault instruction corresponding to a CTT fault micro-operation.

8. The processor of claim 1, further comprising a compiler to insert a first CTT instruction as a first instruction in a first subroutine to be called by the control transfer instruction, the control transfer instruction corresponding to a call instruction.

9. The processor of claim 7, wherein the compiler is to insert a second CTT instruction as a first instruction after the call instruction.

10. The processor of claim 1, further comprising a configuration register to store a CTT state including an enable field to enable the CTT logic, a tracker field to store a state of the CTT logic, and a suppression field to suppress the CTT logic.

11. The processor of claim 1, wherein the CTT instruction comprises a multi-byte opcode, the CTT instruction to be executed as a no operation by the execution unit.

12. The processor of claim 1, wherein the decode unit further comprises a second CTT logic, the CTT logic to operate at a user level and the second CTT logic to operate at a supervisor level.

13. A processor comprising:

an execution logic to execute instructions; and

a control transfer termination (CTT) logic coupled to the execution logic, wherein the CTT logic is to cause a CTT fault to be raised if a target instruction of a control transfer instruction is not a CTT instruction.

14. The processor of claim 13, wherein the processor further comprises a retirement unit, the retirement unit to raise the CTT fault after retirement of the CTT instruction.

15. The processor of claim 13, wherein the CTT instruction comprises a user-level instruction having a multi-byte opcode.

16. The processor of claim 15, wherein the CTT instruction is to execute as a no operation in the execution logic.

17. The processor of claim 13, wherein the processor further comprises a decode unit to decode a CTT suppression instruction to cause the CTT logic to remain in an idle state responsive to a control transfer instruction, to prevent the CTT fault from being raised.

18. The processor of claim 17, wherein the decode unit is further to decode a CTT suppression removal instruction to cause the CTT logic to transition to a wait state responsive to a control transfer instruction.

19. A machine-readable medium having stored thereon instructions, which if performed by a machine cause the machine to perform a method comprising:

decoding a control transfer instruction and decoding a next instruction following the control transfer in a decode unit of a processor;

providing the control transfer instruction and the next instruction to a pipeline of the processor;

retiring the control transfer instruction in a retirement unit of the processor; and

raising a fault via the retirement unit, if the next instruction is not a control transfer termination (CTT) instruction.

20. The machine-readable medium of claim 19, further comprising instructions that cause the machine to handle the fault and to update a state of a CTT logic of the decode unit.

21. The machine-readable medium of claim 20, further comprising instructions that cause the CTT logic to transition into a wait state responsive to the control transfer instruction.

22. The machine-readable medium of claim 21, further comprising instructions that cause the CTT logic to transition into an idle state responsive to the next instruction, wherein the next instruction is a CTT instruction.

23. The machine-readable medium of claim 19, further comprising instructions that cause the machine to provide a CTT fault instruction to the pipeline when the next instruction is not a CTT instruction.

24. The machine-readable medium of claim 19, wherein the CTT instruction is inserted via a binary rewriting tool.

25. A system comprising:

a processor including a front end unit having a control transfer termination (CTT) logic, an execution logic coupled to the front end unit to execute instructions, and a retirement unit coupled to the execution logic, wherein the retirement unit is to raise a CTT fault when a target instruction of a retired control transfer instruction is not a CTT instruction; and

a dynamic random access memory (DRAM) coupled to the processor.

26. The system of claim 25, wherein the DRAM includes a program having an image, the image including a first control transfer instruction to call a first library, the first library having a second control transfer instruction to call a second library, wherein the first library is configured to execute CTT instructions and the second library is not configured to execute CTT instructions.

27. The system of claim 26, wherein the first library includes a first instruction to disable the CTT logic prior to execution of the second control transfer instruction, and a second instruction to enable the CTT logic prior to execution of a return instruction to return to the image.

28. The system of claim 26, wherein the first library includes a first CTT instruction as a target instruction of the first control transfer instruction, and the image includes a second CTT instruction as a target instruction of a return instruction of the first library.

29. The system of claim 25, wherein the processor further comprises a decode unit to decode a CTT suppression instruction to cause the CTT logic to remain in an idle state responsive to a second control transfer instruction to prevent the CTT fault from being raised if a target instruction of the second control transfer instruction is not a CTT instruction, and to thereafter decode a CTT suppression removal instruction to cause the CTT logic to transition to a wait state responsive to a third control transfer instruction.

30. The system of claim 29, wherein the processor further comprises a configuration register to store a CTT state including an enable field to enable the CTT logic and a suppression field to cause the CTT logic to remain in the idle state.