METHOD AND SYSTEM FOR PROVIDING A SMART MEMORY ARCHITECTURE

• US 20140157065A1
• Filed: 07/05/2013
• Published: 06/05/2014
• Est. Priority Date: 02/11/2012
• Status: Active Grant

• Current Assignee: Adrian E. Ong
• Original Assignee: Adrian E. Ong
• Inventors: ONG, Adrian E.
• Granted Patent: US 9,679,664 B2
• Time in Patent Office: Days
• US Class Current: 714/718
• CPC Class Codes: G06F 11/00 Error detection; Error correction; Monitoring error detection, correction or monitoring in information storage based on relative movement between record carrier and transducer G11B20/18; monitoring, i.e. supervising the progress of recording or reproducing G11B27/36; in static stores G11C29/00
• CPC Class Codes: G06F 15/7821 Tightly coupled to memory, e.g. computational memory, smart memory, processor in memory
• CPC Class Codes: G06F 21/00 Security arrangements for protecting computers, components thereof, programs or data against unauthorised activity
• CPC Class Codes: G11C 11/16 using elements in which the storage effect is based on magnetic spin effect
• CPC Class Codes: G11C 13/0002 using resistive RAM [RRAM] elements
• CPC Class Codes: G11C 29/12 Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
• CPC Class Codes: G11C 29/42 using error correcting codes [ECC] or parity check
• CPC Class Codes: G11C 29/44 Indication or identification of errors, e.g. for repair

Abstract

A smart memory system preferably includes a memory including one or more memory chips, and a processor including one or more memory processor chips. The system may include a smart memory controller capable of performing a bit error rate built-in self test. The smart memory control may include bit error rate controller logic configured to control the bit error rate built-in self test. A write error rate test pattern generator may generate a write error test pattern for the bit error rate built-in self test. A read error rate test pattern generator may generate a read error test pattern for the built-in self test. The smart memory controller may internally generate an error rate timing pattern, perform built-in self test, measure the resulting error rate, automatically adjust one or more test parameters based on the measured error rate, and repeat the built-in self test using the adjusted parameters.

Claims

1. A method for providing a bit error rate built-in self test on a memory device, the method comprising:

entering a test mode;

internally generating, by the memory device, an error rate timing pattern;

performing, by the memory device, the bit error rate built-in self test based on the internally generated error rate timing pattern;

measuring an error rate resulting from the bit error rate built-in self test; and

repeating the bit error rate built-in self test.

2. The method of claim 1, further comprising:

adjusting, based on the measured error rate, one or more test parameters,

wherein repeating includes repeating the bit error rate built-in self test using the adjusted parameters.

3. The method of claim 2, wherein:

performing the bit error rate built-in self test includes performing a write error rate test;

measuring includes measuring a write error rate;

adjusting includes adjusting, based on the measured write error rate, the one or more test parameters; and

repeating includes repeating the write error rate test using the adjusted parameters.

4. The method of claim 2, wherein:

performing the bit error rate built-in self test includes performing a read error rate test;

measuring includes measuring a read error rate;

adjusting includes adjusting, based on the measured read error rate, the one or more test parameters; and

repeating includes repeating the read error rate test using the adjusted parameters.

5. The method of claim 1, wherein entering the test mode further comprises:

receiving one or more mode register set commands; and

entering the test mode responsive to the one or more mode register set commands.

6. The method of claim 1, further comprising:

receiving one or more mode register set commands; and

configuring the one or more test parameters responsive to the one or more mode register set commands.

7. The method of claim 6, wherein configuring the one or more test parameters further comprises:

setting at least one of a start voltage, a voltage range, and a voltage step.

8. The method of claim 6, wherein configuring the one or more test parameters further comprises:

setting at least one of a read pulse width and a write pulse width.

9. The method of claim 1, wherein adjusting the one or more test parameters further comprises:

automatically setting a read voltage to a next programmed voltage level.

10. The method of claim 1, wherein adjusting the one or more test parameters further comprises:

automatically setting a write voltage to a next programmed voltage level.

11. The method of claim 1, further comprising:

automatically re-assigning memory space within the memory device when the measured error rate exceeds a predefined threshold.

12. A method for providing a bit error rate built-in self test on a memory device, the method comprising:

performing, by the memory device, at least one of a write error rate built-in self test and a read error rate built-in self test;

analyzing results of the at least one of the write error rate built-in self test and the read error rate built-in self test; and

automatically adjusting one or more test parameters responsive to the analysis.

13. The method of claim 12, wherein automatically adjusting further comprises:

automatically adjusting a voltage level for an address location.

14. The method of claim 12, wherein automatically adjusting further comprises:

automatically adjusting a voltage level for an address segment.

15. The method of claim 12, wherein automatically adjusting further comprises:

automatically adjusting a voltage level for an entire chip associated with the memory device.

16. The method of claim 12, wherein automatically adjusting further comprises:

automatically adjusting a pulse width for an address location.

17. The method of claim 12, wherein automatically adjusting further comprises:

automatically adjusting a pulse width for an address segment.

18. The method of claim 12, wherein automatically adjusting further comprises:

automatically adjusting a pulse width for an entire chip associated with the memory device.

19. A memory device, comprising:

bit error rate control logic configured to control a bit error rate built-in self test;

an on-chip oscillator configured to generate an internal reference clock for the bit error rate built-in self test;

a write error rate test pattern generator configured to generate a write error test pattern for the bit error rate built-in self test; and

a read error rate test pattern generator configured to generate a read error test pattern for the bit error rate built-in self test.

20. The memory device of claim 19, further comprising:

logic configured to count cycles of the bit error rate built-in self test.

21. The memory device of claim 19, further comprising:

a write error rate cycle count register configured to store a number of write cycles; and

a read error rate cycle count register configured to store a number of read cycles.

22. The memory device of claim 19, further comprising:

a pulse width generator circuit; and

a pulse width register configured to provide code to select an intended pulse width delay in the pulse width generator circuit.

23. The memory device of claim 19, further comprising:

a voltage generator; and

a voltage regulator register configured to produce a code to select a voltage bias level in the voltage generator.

24. The memory device of claim 23, further comprising:

a write error counter configured to count a number of write errors of the bit error rate built-in self test; and

a read error counter configured to count a number of read errors of the bit error rate built-in self test.

25. A system for providing a bit error rate built-in self test, comprising:

a bus;

a memory coupled to the bus; and

a smart memory controller, including;

bit error rate control logic configured to control a bit error rate built-in self test;

an on-chip oscillator configured to generate an internal reference clock for the bit error rate built-in self test;

a write error rate test pattern generator configured to generate a write error test pattern for the bit error rate built-in self test; and

a read error rate test pattern generator configured to generate a read error test pattern for the bit error rate built-in self test.

26. The system of claim 25, wherein the smart memory controller further comprises:

logic configured to count cycles of the bit error rate built-in self test.

27. The system of claim 25, wherein the smart memory controller further comprises:

a write error rate cycle count register configured to store a number of write cycles; and

a read error rate cycle count register configured to store a number of read cycles.

28. The system of claim 25, wherein the smart memory controller further comprises:

a pulse width generator circuit; and

a pulse width register configured to provide code to select an intended pulse width delay in the pulse width generator circuit.

29. The system of claim 25, wherein the smart memory controller further comprises:

a voltage generator; and

a voltage regulator register configured to produce a code to select a voltage bias level in the voltage generator.

30. The system of claim 29, wherein the smart memory controller further comprises:

a write error counter configured to count a number of write errors of the bit error rate built-in self test; and

a read error counter configured to count a number of read errors of the bit error rate built-in self test.