APPARATUS AND METHOD FOR APPLYING AT-SPEED FUNCTIONAL TEST WITH LOWER-SPEED TESTER

• US 20140157067A1
• Filed: 11/25/2013
• Published: 06/05/2014
• Est. Priority Date: 11/30/2012
• Status: Active Grant

• Current Assignee: Silicon Motion Incorporated Taiwan (Silicon Motion)
• Original Assignee: Silicon Motion Incorporated Taiwan (Silicon Motion)
• Inventors: Yang, Tsung-Chieh
• Granted Patent: US 9,437,328 B2
• Time in Patent Office: Days
• US Class Current: 714/720
• CPC Class Codes: G06F 11/1048 using arrangements adapted for a specific error detection or correction feature
• CPC Class Codes: G11C 2029/5602 Interface to device under test
• CPC Class Codes: G11C 29/14 Implementation of control logic, e.g. test mode decoders
• CPC Class Codes: G11C 29/56004 Pattern generation
• CPC Class Codes: G11C 29/56012 Timing aspects, clock generation, synchronisation

Abstract

A device under test has a connection interface, a controller, and a functional block. The connection interface is used to receive a test pattern transmitted at a first clock rate and output a functional test result. The controller is used to sample the test pattern by using a second clock rate and accordingly generate a sampled test pattern, wherein the second clock rate is higher than the first clock rate. The functional block is used to perform a designated function upon the sampled test pattern and accordingly generate the functional test result.

Claims

1. A device under test, comprising:

a connection interface, arranged to receive a test pattern transmitted at a first clock rate and output a functional test result;

a controller, arranged to sample the test pattern by using a second clock rate and accordingly generate a sampled test pattern, wherein the second clock rate is higher than the first clock rate; and

a functional block, arranged to perform a designated function upon the sampled test pattern and accordingly generate the functional test result.

2. The device under test of claim 1, wherein the device under test is a flash memory controller chip.

3. The device under test of claim 1, wherein the functional block is an error checking and correction (ECC) circuit.

4. The device under test of claim 3, wherein the designated function is an ECC decoding operation.

5. The device under test of claim 4, wherein the ECC circuit is configured to use shared circuitry to perform an ECC encoding operation and the ECC decoding operation.

6. The device under test of claim 1, further comprising:

a clock generator, arranged to generate an internal reference clock to the controller and the functional block, wherein the internal reference clock has the second clock rate.

7. A tester, comprising:

a test pattern generator, arranged to generate at least one test pattern; and

a connection interface, arranged to transmit the at least one test pattern to the device under test for an at-speed functional test, and receive at least one functional test result from the device under test, wherein the at least one test pattern is transmitted by the connection interface at a first clock rate which is lower than a second clock rate at which the device under test runs the at-speed functional test.

8. The tester of claim 7, wherein each test pattern transmitted by the connection interface includes a one-cycle non-all-zero bit pattern sandwiched by a preceding one-cycle all-zero bit pattern and a following one-cycle all-zero bit pattern.

9. The tester of claim 8, wherein the at least one test pattern includes a first test pattern and a second test pattern, the one-cycle non-all-zero bit pattern included in the first test pattern is identical to the one-cycle non-all-zero bit pattern included in the second test pattern, and the one-cycle non-all-zero bit pattern included in the first test pattern and the one-cycle non-all-zero bit pattern included in the second test pattern are not co-located bit patterns.

10. The tester of claim 8, wherein the at least one test pattern includes a first test pattern and a second test pattern, and the one-cycle non-all-zero bit pattern included in the first test pattern is different from the one-cycle non-all-zero bit pattern included in the second test pattern.

11. The tester of claim 10, wherein the one-cycle non-all-zero bit pattern included in the first test pattern and the one-cycle non-all-zero bit pattern included in the second test pattern have different numbers of l′

s included therein.

12. A method for testing a device under test, comprising:

generating at least one test pattern;

feeding the at least one test pattern transmitted at a first clock rate into the device under test;

sampling the at least one test pattern by using a second clock rate and accordingly generate at least one sampled test pattern, wherein the second clock rate is higher than the first clock rate;

performing a designated function upon the at least one sampled test pattern and accordingly generating at least one functional test result;

outputting the at least one functional test result.

13. The method of claim 12, wherein each test pattern transmitted includes a one-cycle non-all-zero bit pattern sandwiched by a preceding one-cycle all-zero bit pattern and a following one-cycle all-zero bit pattern.

14. The method of claim 13, wherein the step of generating the at least one test pattern comprises:

generating a first test pattern and a second test pattern, wherein the one-cycle non-all-zero bit pattern included in the first test pattern is identical to the one-cycle non-all-zero bit pattern included in the second test pattern, and the one-cycle non-all-zero bit pattern included in the first test pattern and the one-cycle non-all-zero bit pattern included in the second test pattern are not co-located bit patterns.

15. The method of claim 13, wherein the step of generating the at least one test pattern comprises:

generating a first test pattern and a second test pattern, wherein the one-cycle non-all-zero bit pattern included in the first test pattern is different from the one-cycle non-all-zero bit pattern included in the second test pattern.

16. The method of claim 15, wherein the one-cycle non-all-zero bit pattern included in the first test pattern and the one-cycle non-all-zero bit pattern included in the second test pattern have different numbers of l′

s included therein.

17. The method of claim 12, wherein the device under test is a flash memory controller chip.

18. The method of claim 12, wherein the step of performing the designated function comprises:

utilizing an error checking and correction (ECC) circuit to perform the designated function.

19. The method of claim 18, wherein the designated function is an ECC decoding operation.

20. The method of claim 19, wherein the ECC circuit is configured to use shared circuitry to perform an ECC encoding operation and the ECC decoding operation.