ACTIVE MATRIX DISPLAY PANEL WITH GROUND TIE LINES

• US 20140159043A1
• Filed: 03/15/2013
• Published: 06/12/2014
• Est. Priority Date: 12/10/2012
• Status: Active Grant

• Current Assignee: Apple Inc.
• Original Assignee: LuxVue Techonology Corporation (Apple Inc.)
• Inventors: Sakariya, Kapil V., Bibl, Andreas, Hu, Hsin-Hua
• Granted Patent: US 9,029,880 B2
• Time in Patent Office: Days
• US Class Current: 257/59
• CPC Class Codes: G09G 3/32 semiconductive, e.g. using light-emitting diodes [LED]
• CPC Class Codes: H01L 24/95 at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
• CPC Class Codes: H01L 25/0753 the devices being arranged next to each other
• CPC Class Codes: H01L 27/124 with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits wiring structures per se H01L23/52
• CPC Class Codes: H01L 27/156 two-dimensional arrays
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
• CPC Class Codes: H01L 2924/12041 LED
• CPC Class Codes: H01L 2924/12042 LASER
• CPC Class Codes: H01L 2924/12044 OLED
• CPC Class Codes: H01L 33/20 with a particular shape, e.g. curved or truncated substrate
• CPC Class Codes: H01L 33/42 Transparent materials
• CPC Class Codes: H01L 33/62 Arrangements for conducting electric current to or from the semiconductor body, e.g. lead-frames, wire-bonds or solder balls

Abstract

A display panel and a method of forming a display panel are described. The display panel may include a thin film transistor substrate including a pixel area and a non-pixel area. The pixel area includes an array of bank openings and an array of bottom electrodes within the array of bank openings. A ground line is located in the non-pixel area and an array of ground tie lines run between the bank openings in the pixel area and are electrically connected to the ground line in the non-pixel area.

Claims

1. A display panel comprising:

a thin film transistor (TFT) substrate including a pixel area and a non-pixel area, wherein the pixel area includes an array of bank openings and an array of bottom electrodes within the array of bank openings;

a ground line in the non-pixel area; and

an array of ground tie lines running between the bank openings in the pixel area and electrically connected to the ground line in the non-pixel area.

2. The display panel of claim 1, wherein the non-pixel area is around the pixel area.

3. The display panel of claim 2, wherein the ground line is a ground ring in the non-pixel area around the pixel area.

4. The display panel of claim 3, wherein the array of ground tie lines are electrically connected to the ground ring on opposite sides of the pixel area.

5. The display panel of claim 1, wherein the array of bottom electrodes are formed on sidewalls of the corresponding array of bank openings.

6. The display panel of claim 5, wherein the bottom electrodes are reflective to the visible wavelength range.

7. The display panel of claim 6, further comprising a post of solder material on the bottom electrode within each bank opening.

8. The display panel of claim 1, further comprising a patterned insulator layer covering the array of bottom electrodes, and an array of openings in the patterned insulator layer exposing the array of bottom electrodes.

9. The display panel of claim 8, wherein the patterned insulator layer covers edges of the array of bottom electrodes.

10. The display panel of claim 8, further comprising an array of openings in the insulator layer exposing the array of ground tie lines.

11. The display panel of claim 1, further comprising an array of micro LED devices on the array of bottom electrodes within the corresponding array of bank openings.

12. The display panel of claim 11, wherein the micro LED devices are vertical micro LED devices.

13. The display panel of claim 11, wherein the micro LED devices each have a maximum width of 1 μ

m-100 μ

m.

14. The display panel of claim 11, further comprising a transparent passivation layer spanning sidewalls of the array of micro LED devices, wherein the transparent passivation layer does not completely cover a top conductive contact of each micro LED device.

15. The display panel of claim 11, further comprising an array of top electrode layers over and in electrical contact with the array of micro LED devices and the array of ground tie lines.

16. The display panel of claim 15, wherein each top electrode layer electrically connects a plurality of micro LED devices to a single ground tie line.

17. The display panel of claim 15, wherein the array of top electrode layers are formed of a transparent or semi-transparent material.

18. The display panel of claim 15, wherein the array of top electrode layers comprise a material selected from the group consisting of PEDOT and ITO.

19. The display panel of claim 14, further comprising a top electrode layer over and in electrical contact with the array of micro LED devices and the array of ground tie lines through an array of openings over the array of ground tie lines.

20. A method of forming a display panel comprising:

transferring an array of micro LED devices from a carrier substrate to a backplane that comprises;

a thin film transistor (TFT) substrate including a pixel area and a non-pixel area, wherein the pixel area includes an array of bank openings and an array of bottom electrodes within the array of bank openings;

a ground line in the non-pixel area; and

an array of ground tie lines running between the bank openings in the pixel area and electrically connected to the ground line in the non-pixel area;

bonding the array of micro LED devices to the array of bottom electrodes; and

forming a top electrode layer in electrical contact with at least one of the micro LED devices and at least one of the ground tie lines.

21. The method of claim 20, wherein forming the top electrode comprising depositing a top electrode layer over all of the micro LED devices in the array of micro LED devices.

22. The method of claim 20, wherein the top electrode layer spans over a plurality of micro LED devices.

23. The method of claim 20, wherein forming the top electrode layer comprises ink jet printing or screen printing.

24. The method of claim 23, further comprising ink jet printing or screen printing a plurality of separate top electrode layers, each separate top electrode layer spanning over at least one of the micro LED devices and at least one of the ground tie lines.

25. The method of claim 23, wherein each separate top electrode layer spanning over at least one of the micro LED devices and at least one of the ground tie lines is formed within an opening over the at least one of the ground tie lines.

26. The method of claim 20, wherein transferring the array of micro LED devices comprises transferring the array of micro LED devices with an array of electrostatic transfer heads.

27. The method of claim 20, wherein bonding the array of micro LED devices to the array of bottom electrodes comprises the formation of an inter-metallic compound.

28. The method of claim 20, wherein bonding the array of micro LED devices to the array of bottom electrodes comprises liquefying an array of bonding layers formed on the array of bottom electrodes.

29. The method of claim 28, wherein bonding the array of micro LED devices comprises transferring thermal energy from an array of electrostatic transfer heads to the array of bonding layers formed on the array of bottom electrodes.