STABILIZATION STRUCTURE INCLUDING SACRIFICIAL RELEASE LAYER AND STAGING CAVITY

• US 20140159065A1
• Filed: 01/30/2013
• Published: 06/12/2014
• Est. Priority Date: 12/11/2012
• Status: Active Grant

• Current Assignee: Apple Inc.
• Original Assignee: LuxVue Techonology Corporation (Apple Inc.)
• Inventors: Hu, Hsin-Hua, Bibl, Andreas
• Granted Patent: US 9,166,114 B2
• Time in Patent Office: Days
• US Class Current: 257/88
• CPC Class Codes: B81C 99/002 Apparatus for assembling MEMS, e.g. micromanipulators micromanipulators per se B25J7/00
• CPC Class Codes: H01L 21/56 Encapsulations, e.g. encapsulation layers, coatings
• CPC Class Codes: H01L 21/6835 using temporarily an auxiliary support
• CPC Class Codes: H01L 2221/68318 Auxiliary support including means facilitating the separation of a device or wafer from the auxiliary support
• CPC Class Codes: H01L 2221/68368 used in a transfer process involving at least two transfer steps, i.e. including an intermediate handle substrate
• CPC Class Codes: H01L 2221/68381 Details of chemical or physical process used for separating the auxiliary support from a device or wafer
• CPC Class Codes: H01L 2224/16225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/7598 specially adapted for batch processes
• CPC Class Codes: H01L 2224/81 using a bump connector
• CPC Class Codes: H01L 2224/83 using a layer connector
• CPC Class Codes: H01L 2224/95001 involving a temporary auxiliary member not forming part of the bonding apparatus, e.g. removable or sacrificial coating, film or substrate
• CPC Class Codes: H01L 2224/95136 involving guiding structures, e.g. shape matching, spacers or supporting members
• CPC Class Codes: H01L 2224/97 the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
• CPC Class Codes: H01L 24/75 Apparatus for connecting with bump connectors or layer connectors
• CPC Class Codes: H01L 24/80 Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
• CPC Class Codes: H01L 24/81 using a bump connector
• CPC Class Codes: H01L 24/83 using a layer connector
• CPC Class Codes: H01L 24/95 at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
• CPC Class Codes: H01L 25/0753 the devices being arranged next to each other
• CPC Class Codes: H01L 27/153 in a repetitive configuration, e.g. LED bars
• CPC Class Codes: H01L 27/156 : two-dimensional arrays
• CPC Class Codes: H01L 2924/00 : Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/12041 : LED
• CPC Class Codes: H01L 2924/12042 : LASER
• CPC Class Codes: H01L 2924/1461 : MEMS
• CPC Class Codes: H01L 33/0093 : Wafer bonding; Removal of the growth substrate
• CPC Class Codes: H01L 33/48 : characterised by the semiconductor body packages

Abstract

A method and structure for stabilizing an array of micro devices is disclosed. The array of micro devices is held within an array of staging cavities on a carrier substrate. Each micro device is laterally surrounded by sidewalls of a corresponding staging cavity.

Claims

1. A structure comprising:

a carrier substrate;

a stabilization layer including an array of staging cavities on the carrier substrate;

an array of micro devices within the array of staging cavities;

wherein each micro device includes a device layer, and at least a portion of a thickness of the device layer is laterally surrounded by sidewalls of a corresponding staging cavity.

2. The structure of claim 1, wherein each micro device is embedded in a sacrificial release layer within the array of staging cavities.

3. The structure of claim 2, wherein the sacrificial release layer spans over the sidewalls and a bottom surface of each of the staging cavities.

4. The structure of claim 2, wherein the sacrificial release layer comprises an oxide or nitride material.

5. The structure of claim 2, further comprising a sacrificial cap layer over the array of micro devices and the sidewalls of each of the staging cavities.

6. The structure of claim 1, wherein the stabilization layer is formed of a thermoset material.

7. The structure of claim 6, wherein the thermoset material includes benzocyclobutene (BCB).

8. The structure of claim 1, wherein each micro device has a maximum width of 1 to 100 μ

m.

9. The structure of claim 8, wherein each staging cavity has a maximum width of 1 to 100 μ

m.

10. The structure of claim 8, wherein each staging cavity has a maximum width between 0.5 μ

m and 20 μ

m larger than the maximum width of a corresponding micro device within the staging cavity.

11. The structure of claim 8, wherein the sidewalls are 0.5 to 20 μ

m wide.

12. The structure of claim 2, further comprising a conductive contact on a bottom surface of each micro device.

13. The structure of claim 12, wherein each micro device is a micro LED device.

14. The structure of claim 13, further comprising a conductive contact on a top surface of each micro LED device.

15. The structure of claim 12, wherein each micro device is a micro chip.

16. The structure of claim 15, further comprising a plurality of laterally separate conductive contacts on the bottom surface of each micro chip.

17. The structure of claim 16, wherein at least one of the laterally separate conductive contacts on the bottom surface of each micro chip is electrically connected with a landing pad of the respective micro chip.

18. The structure of claim 12, wherein each conductive contact comprises a diffusion barrier and a bonding layer between the diffusion barrier and the sacrificial release layer.

19. A method of forming an array of micro devices comprising:

patterning a device layer on a handle substrate to form an array of laterally separate micro devices;

depositing a sacrificial release layer over the array of micro devices and laterally between the micro devices;

forming a stabilization layer over the sacrificial release layer, which is over the array of micro devices and laterally between the micro devices;

bonding the handle substrate to a carrier substrate; and

removing the handle substrate.

20. The method of claim 19, wherein bonding the handle substrate to the carrier substrate comprises curing the stabilization layer.

21. The method of claim 19, further comprising:

forming an array of conductive contacts over the device layer; and

patterning the device layer on the handle substrate to form the array of laterally separate micro devices underneath the array of conductive contacts.

22. The method of claim 19, comprising partially removing the handle substrate.

23. The method of claim 19, wherein patterning the device layer on the handle substrate to form the array of laterally separate micro devices comprises:

etching through a device layer and stopping on a buried oxide layer.

24. The method of claim 23, wherein removing the handle substrate comprises removing a bulk silicon layer of a silicon-on-insulator (SOI) substrate.

25. The method of claim 19, wherein patterning the device layer on the handle substrate to form the array of laterally separate micro devices comprises etching through:

a p-doped layer;

one or more quantum well layers; and

an n-doped layer.

26. The method of claim 25, further comprising depositing a top conductive contact on the n-doped layer for each micro device.

27. The method of claim 26, further comprising annealing the top conductive contacts to form ohmic contact with the array of laterally separate micro devices.

28. The method of claim 19, further comprising removing the sacrificial release layer.

29. The method of claim 28, wherein removing the sacrificial release layer comprises vapor HF etching.

30. The method of claim 28, wherein removing the sacrificial release layer comprises chlorine-based plasma etching.