SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME

• US 20140159127A1
• Filed: 03/14/2013
• Published: 06/12/2014
• Est. Priority Date: 12/11/2012
• Status: Active Grant

• Current Assignee: SK Hynix Inc.
• Original Assignee: SK Hynix Inc.
• Inventors: LEE, Ki Hong, PYI, Seung Ho, SHON, Hyun Soo
• Granted Patent: US 8,748,970 B1
• Time in Patent Office: Days
• US Class Current: 257/288
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
• CPC Class Codes: H10B 41/20 characterised by three-dimensional arrangements, e.g. with cells on different height levels
• CPC Class Codes: H10B 41/50 characterised by the boundary region between the core region and the peripheral circuit region
• CPC Class Codes: H10B 43/20 characterised by three-dimensional arrangements, e.g. with cells on different height levels
• CPC Class Codes: H10B 43/50 characterised by the boundary region between the core and peripheral circuit regions

Abstract

A semiconductor device having reduced contact region area achieved at least in part by forming pad portions of the word lines using an asymmetric stair shape separately formed in first and second pad structures. Contact region area is reduced when compared with manufacturing processes known in the art. This leads to an increase in device integrity and a less complex manufacturing process.

Claims

1. A semiconductor device comprising:

n first pad structures including first stack layers disposed in a stair configuration, with a step difference being formed between the first pad structures and n being a natural number greater than or equal to 1;

n second pad structures including second stack layers disposed in a stair configuration, with a step difference being formed between the second pad structures; and

a cell structure disposed between the first pad structures and the second pad structures,

wherein, in the first pad structures, at least one uppermost step and at least one lowest step include, respectively, one first stack layer, while the other step includes 2n first stack layers, and

in the second pad structures, at least one uppermost step and at least one lowest step include, respectively, one second stack layer, while the other step includes 2n second stack layers.

2. The semiconductor device of claim 1, wherein a step difference of n layers is formed between facing first and second pad structures.

3. The semiconductor device of claim 1, wherein a step difference is formed between adjoining first pad structures by one layer, and a step difference is formed between adjacent second pad structures by one layer.

4. The semiconductor device of claim 1, wherein at least one uppermost step of the first and the second pad structures is an upper select line, at least one lowest step of the first and the second pad structures is a lower select line, and the other steps are word lines.

5. The semiconductor device of claim 1, wherein an uppermost step or a lowest step of the other steps in the first pad structures is formed with 2n or less first stack layers, and an uppermost step or a lowest step of the other step in the second pad structures is formed with 2n or less second stack layers.

6. The semiconductor device of claim 1, further comprising:

at least one dummy structure located on the lowest step of the other steps in the first and the second pad structures.

7. The semiconductor device of claim 1, wherein the first and the second pad structures are extended in the direction opposite the cell structure.

8. The semiconductor device of claim 1, wherein the cell structure includes:

third stack layers; and

a channel layer passing through the third stack layers.

9. The semiconductor device of claim 8, wherein each of the first stack layers includes a first interlayer insulating layer and a first conductive layer, each of the second stack layers includes a second interlayer insulating layer and a second conductive layer, and each of the third stack layers includes a third interlayer insulating layer and a third conductive layer.

10. The semiconductor device of claim 9, wherein the first to the third conductive layers formed at the same level are connected with one another, and the first to the third interlayer insulating layers formed at the same level are connected with one another.

11. The semiconductor device of claim 9, wherein at least one uppermost conductive layer of the first to the third conductive layers is an upper select line, at least one lowest conductive layer of the first to the third conductive layers is a lower select line, and the other conductive lines are word lines.

12. The semiconductor device of claim 9, wherein the first to the third interlayer insulating layers are formed with substantially the same material, and the first to the third conductive layers are formed with substantially the same material.

13. A memory system comprising:

a memory controller; and

a non-volatile memory device including a semiconductor device comprising;

n first pad structures including first stack layers disposed in a stair configuration, with a step difference being formed between the first pad structures and n being a natural number greater than or equal to 1;

n second pad structures including second stack layers disposed in a stair configuration, with a step difference being formed between the second pad structures; and

a cell structure disposed between the first pad structures and the second pad structures,

wherein, in the first pad structures, at least one uppermost step and at least one lowest step include, respectively, one first stack layer, while the other step includes 2n first stack layers, and

in the second pad structures, at least one uppermost step and at least one lowest step include, respectively, one second stack layer, while the other step includes 2n second stack layers.

14. The memory system of claim 13, wherein a step difference of n layers is formed between facing first and second pad structures.

15. The memory system of claim 13, wherein a step difference is formed between adjoining first pad structures by one layer, and a step difference is formed between adjacent second pad structures by one layer.

16. The semiconductor device of claim 13, wherein at least one uppermost step of the first and the second pad structures is an upper select line, at least one lowest step of the first and the second pad structures is a lower select line, and the other steps are word lines.

17. The memory system of claim 13, wherein an uppermost step or a lowest step of the other steps in the first pad structures is formed with 2n or less first stack layers, and an uppermost step or a lowest step of the other step in the second pad structures is formed with 2n or less second stack layers.

18. The memory system of claim 13, further comprising:

at least one dummy structure located on the lowest step of the other steps in the first and the second pad structures.

19. The memory system of claim 13, wherein the cell structure includes:

third stack layers; and

a channel layer passing through the third stack layers.

20. The memory system of claim 19, wherein each of the first stack layers includes a first interlayer insulating layer and a first conductive layer, each of the second stack layers includes a second interlayer insulating layer and a second conductive layer, and each of the third stack layers includes a third interlayer insulating layer and a third conductive layer.