GATE STRUCTURE IN NON-VOLATILE MEMORY DEVICE
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Abstract
A gate structure of a non-volatile memory device and a method of forming the same including a tunnel oxide layer pattern, a charge trap layer pattern, a blocking dielectric layer pattern having the uppermost layer including a material having a first dielectric constant greater than that of a material included in the tunnel oxide layer pattern, and first and second conductive layer patterns. The gate structure includes a first spacer to cover at least the sidewall of the second conductive layer pattern. The gate structure includes a second spacer covering the sidewall of the first spacer and the sidewall of the first conductive layer pattern and including a material having a second dielectric constant equal to or greater than the first dielectric constant. In the non-volatile memory device including the gate structure, erase saturation caused by back tunneling is reduced.
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Citations
35 Claims
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1-20. -20. (canceled)
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21. A vertical type non-volatile memory device, comprising:
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a channel pattern vertically extending from a substrate; a tunnel oxide layer and a charge trap layer sequentially stacked on a sidewall of the channel pattern; a blocking layer pattern structure including a first portion and a second portion, the first portion being on the charge trap layer, the second portion extending from an end of the first portion to protrude from a sidewall of the channel pattern, and the blocking layer pattern structure having a dielectric constant that is greater than that of the tunnel oxide layer pattern; and at least one word line formed on the first and second portions of the blocking layer pattern structure. - View Dependent Claims (22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32)
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33. A vertical type non-volatile memory device, comprising:
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a channel pattern vertically extending from a substrate, the channel pattern having a pillar shape; a tunnel oxide layer and a charge trap layer sequentially stacked on a sidewall of the channel pattern; insulating interlayer patterns vertically spaced apart from each other on a sidewall of the channel pattern; a blocking layer pattern structure including a first portion and a second portion, the first portion being on the charge trap layer, the second portion extending on surfaces of the insulating interlayer patterns, and the blocking layer pattern structure having a dielectric constant that is greater than that of the tunnel oxide layer pattern; and word lines being between the insulating interlayer patterns and contacting the first and second portions of the blocking layer pattern structure. - View Dependent Claims (34, 35)
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Specification