Power MOS Device Structure

• US 20140159151A1
• Filed: 05/07/2013
• Published: 06/12/2014
• Est. Priority Date: 05/10/2012
• Status: Active Grant

• Current Assignee: CSMC Technologies FAB1 Company Limited (CSMC Manufacturing Company Limited)
• Original Assignee: CSMC Technologies Fab 1 Co., Ltd. (China Resources Microelectronics Limited)
• Inventors: Zhang, Shu, He, Yanqiang, Lo, TseHuang, Wu, HsiaoChia
• Granted Patent: US 9,356,137 B2
• Time in Patent Office: Days
• US Class Current: 257/336
• CPC Class Codes: H01L 23/4824 Pads with extended contours, e.g. grid structure, branch structure, finger structure
• CPC Class Codes: H01L 24/02 Bonding areas on insulating substrates, e.g. chip carriers, H01L23/49816, H01L23/49838, H01L23/5389; Manufacturing methods related thereto
• CPC Class Codes: H01L 24/05 of an individual bonding area
• CPC Class Codes: H01L 24/06 of a plurality of bonding areas
• CPC Class Codes: H01L 24/07 Structure, shape, material or disposition of the bonding areas after the connecting process
• CPC Class Codes: H01L 24/08 of an individual bonding area
• CPC Class Codes: H01L 24/09 of a plurality of bonding areas
• CPC Class Codes: H01L 29/7816 Lateral DMOS transistors, i.e. LDMOS transistors
• CPC Class Codes: H01L 29/7835 with asymmetrical source and drain regions, e.g. lateral high-voltage MISFETs with drain offset region, extended drain MISFETs
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/1306 Field-effect transistor [FET]
• CPC Class Codes: H01L 2924/13091 Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]

Abstract

Various embodiments of a power MOS device structure are disclosed. In one aspect, a power MOS device structure includes a plurality of LDMOS and a plurality of bonding pads. The basic units of LDMOS are coupled in parallel and electrically coupled to the bonding pads to couple to a gate terminal, a source terminal, a drain terminal and a substrate of each of the basic units of LDMOS. The basic units of LDMOS are disposed below the bonding pads. The bonding pads include a single layer of metal with a thickness of 3.5 um to 4.5 um and a width of 1.5 um to 2.5 um. The region below the bonding pads of the power MOS device of the present disclosure is utilized to increase the number of basic units of LDMOS, thereby effectively reducing the on-resistance.

Claims

1. A power MOS device structure, comprising:

a plurality of basic units of lateral double-diffused metal-oxide semiconductor (LDMOS); and

a plurality of bonding pads, wherein;

the basic units of LDMOS are coupled in parallel and electrically coupled to the bonding pads to couple to a gate terminal, a source terminal, a drain terminal and a substrate of each of the basic units of LDMOS;

the basic units of LDMOS are disposed below the bonding pads; and

the bonding pads include a single layer of metal with a thickness of 3.5 um to 4.5 um and a width of 1.5 um to 2.5 um.

2. The power MOS device structure of claim 1, further comprising a first metal layer disposed between the plurality of basic units of LDMOS and the plurality of bonding pads, wherein the basic units of LDMOS, the first metal layer and the bonding pads are electrically coupled by metal plugs.

3. The power MOS device structure of claim 1, wherein the plurality of bonding pads include a gate bonding pad, a source bonding pad, a drain bonding pad, and a substrate bonding pad that are coupled to the gate terminal, source terminal, drain terminal, and source terminal of each of the plurality of basic units of LDMOS which are coupled in parallel.

4. The power MOS device structure of claim 1, wherein the single layer of metal comprises aluminum-copper metal or aluminum-silicon-copper metal.

5. The power MOS device structure of claim 1, wherein plurality of bonding pads further comprises a barrier layer below the single layer of metal.

6. The power MOS device structure of claim 5, wherein the barrier layer comprises a titanium layer and a titanium nitride layer, a thickness of the titanium layer being 300 Å

˜

600 Å and

a thickness of the titanium nitride layer being 300 Å

˜

800 Å

.

7. The power MOS device structure of claim 1, wherein the plurality of bonding pads further comprise an anti-reflection layer above the single layer of metal.

8. The power MOS device structure of claim 7, wherein the anti-reflection layer comprises a titanium layer and a titanium nitride layer, a thickness of the titanium layer being 100 Å

˜

400 Å and

a thickness of the titanium nitride layer being 250 Å

˜

400 Å

.

9. The power MOS device structure of claim 1, further comprising a passivation layer over a surface of the power MOS device structure with one or more openings exposing the plurality of bonding pads.

10. The power MOS device structure of claim 9, wherein the passivation layer comprises a layer of plasma-rich silicon oxide film having a thickness of 1 kÅ

to 2 kÅ

, a layer of high-density plasma silicon dioxide film having a thickness of 10 kÅ

20 kÅ and

disposed over the layer of plasma-rich silicon oxide film, and a layer of plasma silicon nitride film having a thickness of 7 kÅ

to 11 kÅ and

disposed over the layer of high-density plasma silicon dioxide film.