CURRENT MODE PWM BOOST CONVERTER
First Claim
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1. A current mode pulse width modulation (PWM) converter, comprising:
- a boost circuit configured to receive an input voltage, and boost the input voltage to an output voltage, the boost circuit comprising an inductor and a switch configured to control flow of a current flowing through the inductor;
a pseudo random clock generating unit configured to generate a clock signal, and vary a frequency of the clock signal;
a voltage divider configured to receive the output voltage, and divide the output voltage to a division voltage;
a reset signal generating circuit configured to generate a reset signal based on the division voltage and the current flowing through the boost inductor; and
a driving signal generating circuit configured to receive the clock signal and the reset signal, and generate a driving signal of the switch based on the clock signal and the reset signal, the driving signal having a low-to-high transition corresponding to a low-to-high transition of the clock signal and having a high-to-low transition corresponding to a low-to-high transition of the reset signal, andwherein in response to the pseudo random clock generating unit varying the frequency of the clock signal from a first frequency of the clock signal to a second frequency of the clock signal, the reset signal generating circuit controls activation time of the reset signal by varying a frequency of the clock signal such that a duty ratio of the driving signal based on the first frequency of the clock signal is substantially equal to a duty ratio of the driving signal based on the second frequency of the clock signal.
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Abstract
A current mode PWM converter configured to maintain a duty ratio of a driving signal for driving a boost circuit boosting an input voltage to an output voltage when a frequency of a clock signal for generating the driving signal is varied.
35 Citations
15 Claims
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1. A current mode pulse width modulation (PWM) converter, comprising:
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a boost circuit configured to receive an input voltage, and boost the input voltage to an output voltage, the boost circuit comprising an inductor and a switch configured to control flow of a current flowing through the inductor; a pseudo random clock generating unit configured to generate a clock signal, and vary a frequency of the clock signal; a voltage divider configured to receive the output voltage, and divide the output voltage to a division voltage; a reset signal generating circuit configured to generate a reset signal based on the division voltage and the current flowing through the boost inductor; and a driving signal generating circuit configured to receive the clock signal and the reset signal, and generate a driving signal of the switch based on the clock signal and the reset signal, the driving signal having a low-to-high transition corresponding to a low-to-high transition of the clock signal and having a high-to-low transition corresponding to a low-to-high transition of the reset signal, and wherein in response to the pseudo random clock generating unit varying the frequency of the clock signal from a first frequency of the clock signal to a second frequency of the clock signal, the reset signal generating circuit controls activation time of the reset signal by varying a frequency of the clock signal such that a duty ratio of the driving signal based on the first frequency of the clock signal is substantially equal to a duty ratio of the driving signal based on the second frequency of the clock signal. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10)
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11. A current mode PWM converter, comprising:
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a boost circuit configured to receive an input voltage, and boost the input voltage to an output voltage, the boost circuit comprising an inductor and a switch configured to control flow of a current flowing through the inductor; a voltage divider configured to receive the output voltage, and divide the output voltage to a division voltage; an error amplifier configured to compare the division voltage and a reference voltage, and to generate an error signal based on a result of comparing the division voltage and the reference voltage; a pseudo random clock generating unit configured to generate a clock signal, and vary a frequency of the clock signal; a feedback signal generating circuit configured to add a slope compensation ramp signal and a sensing signal obtained through sensing of the current flowing through the inductor to generate a feedback signal based on a result of adding the slope compensation ramps signal and the sensing signal; a comparator configured to compare the error signal and the feedback signal, and to output a reset signal based on a result of comparing the error signal and the feedback signal; and a driving signal generating circuit configured to generate a driving signal for driving the switch in response to the clock signal and the reset signal output by the comparator, wherein a slope of the slope compensation ramp signal is varied according to the variation of the frequency of the clock signal. - View Dependent Claims (12, 13)
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14. A current mode PWM converter, comprising:
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a boost circuit configured to receive an input voltage, and boost the input voltage to an output voltage, the boost circuit comprising an inductor and a switch configured to control flow of a current flowing through the inductor; a pseudo random clock generating unit configured to generate a clock signal, and vary a frequency of the clock signal; a voltage divider configured to receive the output voltage, and divide the output voltage to a division voltage; an error amplifier configured to compare the division voltage and a reference voltage, and to generate an error signal based on a result of comparing the division voltage and the reference voltage; an error signal compensation circuit configured to vary a voltage level of the error signal according to variation of the frequency of the clock signal; a feedback signal generating circuit configured to add a slope compensation ramp signal and a sensing signal obtained through sensing of the current flowing through the inductor, and to generate a feedback signal based a result of adding the slope compensation ramp signal and the sensing signal; a comparator configured to compare an output of the error signal compensation circuit and the feedback signal; and a driving signal generating circuit configured to generate a driving signal for driving the switch based on the clock signal and an output of the comparator. - View Dependent Claims (15)
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Specification