INTEGRATED CIRCUIT INCLUDING CIRCUITS DRIVEN IN DIFFERENT VOLTAGE DOMAINS
First Claim
1. An integrated circuit comprising:
- a logic circuit configured to be driven by a first power supply voltage having a first power supply voltage level; and
a memory circuit configured to be driven by a second power supply voltage having a second power supply voltage level different from the first power supply voltage level, the memory circuit comprising a circuit configured to interface with the logic circuit,wherein the circuit is configured to be supplied with power at the second power supply voltage level in response to an output signal, and configured to shift a level of a signal having the first power supply voltage level received from the logic circuit to the second power supply voltage level.
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Accused Products
Abstract
Provided is an integrated circuit including circuits driven in different voltage domains. The integrated circuit includes a logic circuit configured to be driven by a first power supply voltage having a first power supply voltage level, and a memory circuit configured to be driven by a second power supply voltage having a second power supply voltage level different from the first power supply voltage level. The memory circuit includes a circuit configured to interface with the logic circuit, configured to be supplied with power at the second power supply voltage level in response to an output signal, and configured to shift a level of a signal having the first power supply voltage level received from the logic circuit to the second power supply voltage level. The first power supply voltage corresponds to a first voltage domain, and the second power supply voltage corresponds to a second voltage domain.
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Citations
26 Claims
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1. An integrated circuit comprising:
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a logic circuit configured to be driven by a first power supply voltage having a first power supply voltage level; and a memory circuit configured to be driven by a second power supply voltage having a second power supply voltage level different from the first power supply voltage level, the memory circuit comprising a circuit configured to interface with the logic circuit, wherein the circuit is configured to be supplied with power at the second power supply voltage level in response to an output signal, and configured to shift a level of a signal having the first power supply voltage level received from the logic circuit to the second power supply voltage level. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9)
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10. A decoder comprising:
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a logic gate configured to decode a plurality of first input signals having a first power supply voltage level and generate a first output signal at an output node, the first output signal having a second power supply voltage level different from the first power supply voltage level; and an inverter configured to invert the first output signal and generate a second output signal at the second power supply voltage level, wherein the decoder is configured to receive a first clock signal configured to control precharging the output node at a first logic level of the first clock signal and evaluate the output node at a second logic level of the first clock signal, and wherein the second output signal is received at the logic gate. - View Dependent Claims (11, 12, 13, 14, 15)
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16. A memory comprising:
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an address decoder configured to decode a plurality of address input signals at a first power supply voltage level and generate a first address decoding signal at an output node at a second power supply voltage level different from the first power supply voltage level; and an inverter configured to invert the first address decoding signal and generate a second address decoding signal at the second power supply voltage level, wherein the memory is configured to receive a first clock signal configured to control precharging the output node at a first phase of the first clock signal and evaluate the output node at a second phase of the first clock signal, and wherein the second address decoding signal is received at a logic gate. - View Dependent Claims (17, 18, 19, 20, 21, 22)
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23. A method of processing data by an integrated circuit comprising a logic circuit and a memory circuit, the method comprising:
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generating, by the logic circuit, control signals having a first power supply voltage level which are used to control the memory circuit, and transmitting the control signals to the memory circuit; shifting, by the memory circuit, levels of the controls signals to a second power supply voltage level which is different from the first power supply voltage level; and performing, by the memory circuit, read or write operations according to the control signals having the shifted levels. - View Dependent Claims (24, 25, 26)
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Specification