VARIABLE CAPACITANCE CIRCUIT

• US 20140159829A1
• Filed: 02/27/2013
• Published: 06/12/2014
• Est. Priority Date: 12/10/2012
• Status: Abandoned Application

• Current Assignee: Samsung Electro-Mechanics Co., Ltd. (Samsung Group)
• Original Assignee: Samsung Electro-Mechanics Co., Ltd. (Samsung Group)
• Inventors: CHOI, Jae Hyouck, KIM, Jeong Hoon, JEONG, Chan Yong, PARK, Sang Wook, PARK, Sung Hwan
• Application Number:
  US13/779,649
• Publication Number:
  US 20140159829A1
• Time in Patent Office: Days
• US Class Current: 333/32
• CPC Class Codes: H03H 11/481 Simulating capacitances
• CPC Class Codes: H03H 7/38 Impedance-matching networks

Abstract

There is provided a variable capacitance circuit, including a capacitance circuit unit connected between a first terminal and a second terminal and providing a preset capacitance, a variable capacitance circuit unit including a first transistor connected to the capacitance circuit unit in series between the first terminal and the second terminal, the first transistor being operated according to a gate voltage, and a switching unit connected between a body of the first transistor and an input terminal of a preset body voltage, wherein the switching unit is turned off when the first transistor is turned on and turned on when the first transistor is turned off.

Claims

1. A variable capacitance circuit, comprising:

a capacitance circuit unit connected between a first terminal and a second terminal and providing capacitance;

a variable capacitance circuit unit including a first transistor connected to the capacitance circuit unit in series between the first terminal and the second terminal, the first transistor being operated according to a gate voltage; and

a switching unit connected between a body of the first transistor and an input terminal of a preset body voltage,

wherein the switching unit is turned off when the first transistor is turned on and turned on when the first transistor is turned off.

2. The variable capacitance circuit of claim 1, wherein the capacitance circuit unit includes:

at least one capacitance element, and

the at least one capacitance element is one of a metal oxide semiconductor (MOS) capacitor and a metal-insulator-metal (MIM) capacitor.

3. The variable capacitance circuit of claim 1, wherein the variable capacitance circuit unit includes:

a transistor circuit unit including the first transistor and second through n-th transistors connected to the first transistor in series, the first through n-th transistors being operated according to the gate voltage;

a gate resistor unit including first through n-th gate resistors connected between respective gates of the first through n-th transistors and an input terminal of the gate voltage; and

a body resistor unit including first through n-th body resistors connected between respective bodies of the first through n-th transistors and an input terminal of the body voltage.

4. The variable capacitance circuit of claim 3, wherein in the transistor circuit unit, the amount of transistors connected in series is determined according to a power differential between the first terminal and the second terminal.

5. The variable capacitance circuit of claim 3, wherein the first through n-th transistors are configured of one of a metal oxide semiconductor field-effect transistor (MOSFET) and a metal semiconductor field effect transistor (MESFET).

6. The variable capacitance circuit of claim 3, wherein the switching unit is configured of a switching transistor connected between a common node connected to the respective bodies of the first through n-th transistors and the input terminal of the body voltage, and is turned off when the first to n-th transistors are turned on and turned on when the first through n-th transistors are turned off, according to preset switching voltage.

7. A variable capacitance circuit, comprising:

a capacitance circuit unit connected between a first terminal and a second terminal and providing a preset capacitance;

a variable capacitance circuit unit including a first transistor connected to the capacitance circuit unit in series between the first terminal and the second terminal, the first transistor being operated according to a gate voltage;

a switching unit connected between a body of the first transistor and an input terminal of a preset body voltage; and

a control unit turning the first transistor on and turning the switching unit off in a preset floating body mode and turning the first transistor off and turning the switching unit on in a preset contact body mode.

8. The variable capacitance circuit of claim 7, wherein the capacitance circuit unit includes:

at least one capacitance element, and

the at least one capacitance element is one of a metal oxide semiconductor (MOS) capacitor and a metal-insulator-metal (MIM) capacitor.

9. The variable capacitance circuit of claim 7, wherein the variable capacitance circuit unit includes:

a transistor circuit unit including the first transistor and second through n-th transistors connected to the first transistor in series, the first through n-th transistors being operated according to the gate voltage;

a gate resistor unit including first through n-th gate resistors connected between respective gates of the first through n-th transistors and an input terminal of the gate voltage; and

a body resistor unit including first through n-th body resistors connected between respective bodies of the first through n-th transistors and an input terminal of the body voltage.

10. The variable capacitance circuit of claim 9, wherein in the transistor circuit unit, the amount of transistors connected in series is determined according to a power differential between the first terminal and the second terminal.

11. The variable capacitance circuit of claim 9, wherein the first through n-th transistors are configured of one of a metal oxide semiconductor field-effect transistor (MOSFET) and a metal semiconductor field effect transistor (MOSFET).

12. The variable capacitance circuit of claim 9, wherein the switching unit is configured of a switching transistor connected between a common node connected to the respective bodies of the first through n-th transistors and the input terminal of the body voltage and is turned off when the first to n-th transistors are turned on and turned on when the first through n-th transistors are turned off, according to a control from the control unit.