ARRAY SUBSTRATE FOR TFT-LED, METHOD OF MANUFACTURING THE SAME, AND DISPLAY DEVICE

• US 20140160416A1
• Filed: 12/04/2013
• Published: 06/12/2014
• Est. Priority Date: 12/06/2012
• Status: Abandoned Application

• Current Assignee: Beijing BOE Display Technology Co Ltd (BOE Technology Group Co., Ltd.), BOE Technology Group Co., Ltd.
• Original Assignee: Beijing BOE Display Technology Co Ltd (BOE Technology Group Co., Ltd.), BOE Technology Group Co., Ltd.
• Inventors: Cao, Kun, Wang, Xiao
• Application Number:
  US14/096,798
• Publication Number:
  US 20140160416A1
• Time in Patent Office: Days
• US Class Current: 349/139
• CPC Class Codes: G02F 1/133397 for suppressing after-image or image-sticking
• CPC Class Codes: G02F 1/134363 for applying an electric field parallel to the substrate, i.e. in-plane switching [IPS]
• CPC Class Codes: G02F 1/13624 having more than one switching element per pixel

Abstract

An array substrate, a method of manufacturing the same, and a display device are provided to effectively eliminate the afterimage phenomenon and improve the display quality of display device. A pixel electrode, a common electrode, a first TFT and a second TFT are provided in a sub-pixel region defined by Nth and (N+1)th gate lines of a plurality of gate lines and two data lines of the plurality of data lines, and a multi-dimensional electric field is formed when the pixel electrode and the common electrode are powered. A first gate electrode of the first TFT is connected to the (N+1)th gate line, a first source electrode of a first TFT is connected to one of the two data lines, a first drain electrode of the first TFT is connected to the pixel electrode; a second gate electrode of a second TFT is connected to the Nth gate line, a second drain electrode of the second TFT is connected to the pixel electrode, a second source electrode of the second TFT is connected to the common electrode; and the Nth gate line comprises any one of the plurality of gate lines except the last one, and during a gate line scanning process for one frame in the array substrate, the Nth gate line is always scanned in advance of the (N+1)th gate line.

Claims

1. An array substrate for using in a TFT-LCD comprising:

a transparent substrate;

a plurality of gate lines and a plurality of data lines positioned crosswise on the transparent substrate to define a plurality of sub-pixel regions; and

a pixel electrode, a common electrode, a first TFT and a second TFT provided in a sub-pixel region defined by the Nth and (N+1)th gate lines of the plurality of gate lines and two data lines of the plurality of data lines, and the pixel electrode and the common electrode forming a multi-dimensional electric field when powered;

wherein a first gate electrode of the first TFT is connected to the (N+1)th gate line, a first source electrode of the first TFT is connected to one of the two data lines, a first drain electrode of the first TFT is connected to the pixel electrode;

a second gate electrode of the second TFT is connected to the Nth gate line, a second drain electrode of the second TFT is connected to the pixel electrode, a second source electrode of the second TFT is connected to the common electrode; and

the Nth gate line comprises any one of the plurality of gate lines except the last one, and during a gate line scanning process for one frame in the array substrate, the Nth gate line is always scanned in advance of the (N+1)th gate line.

2. The array substrate according to claim 1, wherein the common electrode and the pixel electrode are positioned in the same layer, the common electrode comprises a plurality of first strip electrodes, the pixel electrode comprises a plurality of second strip electrodes, the first strip electrodes and the second strip electrodes are arranged alternatively.

3. The array substrate according to claim 1, wherein the common electrode and the pixel electrode are positioned in different layers, and wherein the electrode positioned in an upper layer comprises a plurality of strip electrodes, and the electrode positioned in a lower layer comprises a plurality of strip electrodes or a plate electrode.

7. A display device, comprising a color film substrate and the array substrate according to claim 1 assembled by a cell assembly process.

8. The display device according to claim 7, wherein the common electrode and the pixel electrode are positioned in the same layer, the common electrode comprises a plurality of first strip electrodes, the pixel electrode comprises a plurality of second strip electrodes, the first strip electrodes and the second strip electrodes are arranged alternatively.

9. The display device according to claim 7, wherein the common electrode and the pixel electrode are positioned in different layers, and wherein the electrode positioned on the upper layer comprises a plurality of strip electrodes, and the electrode positioned in a lower layer comprises a plurality of strip electrodes or a plate electrode.

4. A method for manufacturing an array substrate used in a TFT-LCD comprising steps of:

forming a plurality of gate lines, a plurality of data lines, a plurality of pixel electrodes, a plurality of common electrodes, a plurality of first TFTs and a plurality of second TFTs on a transparent substrate;

wherein a sub-pixel region is defined by the Nth and (N+1)th gate lines of the plurality of gate lines and two data lines of the plurality of data lines, one pixel electrode, one common electrode, one first TFT and one second TFT are included in the sub-pixel region, and the pixel electrode and the common electrode form a multi-dimensional electric field when powered;

a first gate electrode of the first TFT is connected to the (N+1)th gate line, a first source electrode of the first TFT is connected to one of the two data lines, a first drain electrode of the first TFT is connected to the pixel electrode;

a second gate electrode of the second TFT is connected to the Nth gate line, a second drain electrode of the second TFT is connected to the pixel electrode, a second source electrode of the second TFT is connected to the common electrode; and

the Nth gate line comprises any one of the plurality of gate lines except the last one, and during a gate line scanning process for one frame in the array substrate, the Nth gate line is always scanned in advance of the (N+1)th gate line.

5. The method according to claim 4, wherein the step of forming the plurality of gate lines, the plurality of data lines, the plurality of pixel electrodes, the plurality of common electrodes, the plurality of first TFTs and the plurality of second TFTs in the transparent substrate comprises steps of:

forming a gate metal film on the transparent substrate, and at least forming the Nth gate line, the (N+1)th gate line, the first gate electrode and the second gate electrode through patterning process;

wherein the first gate electrode is electrically connected to the (N+1)th gate line, and the second gate electrode is electrically connected to the Nth gate line;

forming a gate insulation layer on the transparent substrate to cover the first and the second gate electrodes;

forming an active layers at positions on the gate insulation layer corresponding to the first gate electrode and the second gate electrode;

forming a transparent conductive film on the gate insulation layer in which the active layers are formed, and forming the common electrode through patterning process;

forming a first passivation layer on the gate insulation layer to cover the common electrode and the active layers, and forming a first via passing through the first passivation layer on the common electrode through patterning process;

forming a metal film on the first passivation layer, and at least forming the first source electrode, the first drain electrode, the second source electrode, the second drain electrode and the data line through patterning process, wherein the second source electrode is connected to the common electrode through the first via;

forming a second passivation layer film on the first passivation layer, and forming second vias passing through the second passivation layer on first drain electrode and the second drain electrode through patterning process, respectively; and

forming a transparent conductive film on the second passivation layer, and forming the pixel electrode through patterning process, wherein the pixel electrode is connected to the first drain electrode and the second drain electrode, respectively, through the second vias in the second passivation layer.

6. The method according to claim 4, wherein the step of forming the plurality of gate lines, the plurality of data lines, the plurality of pixel electrodes, the plurality of common electrodes, the plurality of first TFTs and the plurality of second TFTs in the transparent substrate comprises steps of:

forming a gate metal film on the transparent substrate, and at least forming the Nth gate line, the (N+1)th gate line, the first gate electrode and the second gate electrode through patterning process;

wherein the first gate electrode is electrically connected to the (N+1)th gate line, and the second gate electrode is electrically connected to the Nth gate line;

forming a gate insulation layer on the transparent substrate to cover the first and the second gate electrodes;

forming active layers at positions on the gate insulation layer corresponding to the first gate electrode and the second gate electrode;

forming a first passivation layer film on the gate insulation layer, in which the active layers are formed, to cover the active layers;

forming a metal film on the first passivation layer, and at least forming the first source electrode, the first drain electrode, the second source electrode, the second drain electrode and the data line through patterning process;

forming a second passivation layer film on the first passivation layer, and forming, through patterning process, first vias passing through the second passivation layer on the first drain electrode and the second drain electrode, respectively, and a second via passing through the second passivation layer on the second source electrode; and

forming a transparent conductive film on the second passivation layer, and forming the pixel electrode and the common electrode that are arranged alternatively through patterning process, wherein the pixel electrode is connected respectively to the first drain electrode and the second drain electrode through the first vias, and the common electrode is connected to the second source electrode through the second via.