NON-UNIFORM SUBSTRATE STACKUP

• US 20140160707A1
• Filed: 12/06/2012
• Published: 06/12/2014
• Est. Priority Date: 12/06/2012
• Status: Active Grant

• Current Assignee: Intel Corporation
• Original Assignee: Intel Corporation
• Inventors: Zhang, Zhichao, Wu, Tao, Qian, Zhiguo, Aygun, Kemal
• Granted Patent: US 9,232,639 B2
• Time in Patent Office: Days
• US Class Current: 361/767
• CPC Class Codes: H01L 21/4846 Leads on or in insulating or insulated substrates, e.g. metallisation H01L21/4821 takes precedence; metallisation of ceramics in general C04B41/51; printed circuits H05K3/00
• CPC Class Codes: H01L 23/49822 Multilayer substrates multilayer metallisation on monolayer substrate H01L23/498
• CPC Class Codes: H01L 23/49838 Geometry or layout
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
• CPC Class Codes: H05K 1/0216 Reduction of cross-talk, noise or electromagnetic interference grounding H05K1/0215
• CPC Class Codes: H05K 1/0298 Multilayer circuits
• CPC Class Codes: H05K 2201/0191 wherein the thickness of the dielectric plays an important role
• CPC Class Codes: H05K 2201/0352 Differences between the conductors of different layers of a multilayer
• CPC Class Codes: H05K 2201/09736 Varying thickness of a single conductor; Conductors in the same plane having different thicknesses
• CPC Class Codes: H05K 2201/10378 Interposers
• CPC Class Codes: H05K 2201/10674 Flip chip
• CPC Class Codes: H05K 2201/10734 Ball grid array [BGA]; Bump grid array
• CPC Class Codes: Y10T 29/49155 Manufacturing circuit on or in base

Abstract

Some embodiments described herein include apparatuses and methods of forming such apparatuses. One such embodiment may include a routing arrangement having pads to be coupled to a semiconductor die, with a first trace coupled to a first pad among the pads, and a second trace coupled to a second pad among the pads. The first and second traces may have different thicknesses. Other embodiments including additional apparatuses and methods are described.

Claims

1. A routing arrangement comprising:

pads to be coupled to a die;

a first trace coupled to a first pad among the pads, the first trace having a first thickness; and

a second trace coupled to a second pad among the pads, the second trace having a second thickness, wherein the second thickness is different from the first thickness.

2. The routing arrangement of claim 1, wherein the first trace is located in a first layer of a substrate, and the second trace is located in a second layer of the substrate.

3. The routing arrangement of claim 1, wherein the first trace and the second trace are located on a same layer of a substrate.

4. The routing arrangement of claim 1, further comprising:

a first dielectric directly contracting the first trace; and

a second dielectric directly contracting the second trace, wherein the first and second dielectrics layers have different thicknesses.

5. The routing arrangement of claim 1, further comprising:

a third trace having a third thickness equal to the first thickness of the first trace, wherein the first and third traces are located in first same layer of a substrate; and

a fourth trace having a fourth thickness equal to the second thickness of the second trace, wherein the second and fourth traces are located in a second layer of a substrate.

6. The routing arrangement of claim 1, further comprising:

a third trace having a third thickness different form the first thickness of the first trace, wherein the first and third traces are located in first same layer of a substrate; and

a fourth trace having a fourth thickness different from the second thickness of the second trace, wherein the second and fourth traces are located in a second layer of a substrate.

7. The routing arrangement of claim 1, wherein the first trace and the second trace include micro-strips.

8. The routing arrangement of claim 1, wherein the first trace and the second trace include strip-lines.

9. The routing arrangement of claim 1, wherein the first trace includes a micro-strip and the second trace includes a strip-line.

10. The routing arrangement of claim 1, further comprising at least one of a ground plane and a power plane between the first and second traces.

11. The routing arrangement of claim 1, further comprising additional traces in a layer between the first and second traces and arranged to carry at least one of power and ground.

12. An electronic assembly comprising:

a die; and

a substrate coupled to the die, the substrate including;

a first layer including a first trace, the first trace having a first thickness;

a second layer including a second trace, the second trace having a second thickness, wherein the second thickness is different from the first thickness; and

a third layer including at least one of a ground plane and a power plane layer.

13. The electronic assembly of claim 12, wherein the first trace is coupled to a pad of the substrate, and the pad is located outside a footprint of the die.

14. The electronic assembly of claim 13, wherein the first trace is coupled to an additional pad of the substrate, and the pad is located inside the footprint of the die.

15. The electronic assembly of claim 14, wherein the first layer includes an additional trace coupled to an additional pad of the substrate, and the additional pad is located outside the footprint of the die.

16. The electronic assembly of claim 12, wherein the first and second traces are arranged to carry differential types of signals.

17. The electronic assembly of claim 12, wherein the first and second traces are arranged to carry single-ended and differential signals.

18. The electronic assembly of claim 12, wherein at least one of the ground plane and the power plane includes a thickness different from one of the first and second thicknesses.

19. The electronic assembly of claim 12, further comprising electrical connections coupled between the substrate and a circuit board.

20. The electronic assembly of claim 12, wherein the die includes a processor.

21. A method comprising:

forming a first trace in a substrate; and

forming a second trace in the substrate, wherein the first and second traces are formed such that the first and second traces have different thicknesses.

22. The method of claim 21, wherein the first and second traces are formed in a same layer of the substrate.

23. The method of claim 21, wherein the first and second traces are formed in a same layer of the substrate, and the first trace is formed before the second trace is formed.

24. The method of claim 21, wherein the first and second traces are formed in different layers of the substrate.

25. The method of claim 21, further comprising:

forming a first dielectric directly contacting the first trace; and

forming a second dielectric directly contacting the second trace, wherein the first and second dielectrics have different thicknesses.