Adaptive Operation of Multi Level Cell Memory

• US 20140160842A1
• Filed: 01/14/2013
• Published: 06/12/2014
• Est. Priority Date: 12/06/2012
• Status: Active Grant

• Current Assignee: SanDisk Technologies LLC (Western Digital Corporation)
• Original Assignee: Sandisk Technologies Incorporated (Western Digital Corporation)
• Inventors: Yang, Nian Niles, Avila, Chris Nga Yee, Takafuji, Ryan Chiezo
• Granted Patent: US 8,995,184 B2
• Time in Patent Office: Days
• US Class Current: 365/185.03
• CPC Class Codes: G11C 11/5621 using charge storage in a floating gate
• CPC Class Codes: G11C 16/0483 comprising cells having several storage transistors connected in series
• CPC Class Codes: G11C 16/3418 Disturbance prevention or evaluation; Refreshing of disturbed memory data
• CPC Class Codes: G11C 16/349 Arrangements for evaluating degradation, retention or wearout, e.g. by counting erase cycles

Abstract

A Multi Level Cell (MLC) nonvolatile memory is tested and, if it fails to meet an MLC specification, is reconfigured for operation as an SLC memory by assigning two of the MLC memory cell states as SLC states in a first SLC mode, according to predefined sets of criteria. Subsequently, different MLC memory cell states are assigned as SLC states in a second SLC mode.

Claims

1. An adaptable method of operating a plurality of cells of a Multi-Level Cell (MLC) nonvolatile memory array in different binary modes, comprising:

assigning a first binary state to a first MLC state of three or more MLC states;

assigning a second binary state to a second MLC state of the three or more MLC states in a first mode; and

subsequently reassigning the second binary state from the second MLC state to a third MLC state of the three or more MLC states in a second mode.

2. The adaptable method of claim 1 wherein the first MLC state is an erased state, and the second MLC state corresponds to more charge in a charge storage element of a memory cell than the third MLC state.

3. The adaptable method of claim 2 wherein the second MLC state corresponds to the most charge in a charge storage element of any of the three or more MLC states.

4. The adaptable method of claim 1 further comprising subsequently reassigning the second binary state from the third MLC state to a fourth MLC state of the three or more MLC states, the third MLC state corresponding to more charge in a charge storage element of a memory cell than the fourth MLC state.

5. The adaptable method of claim 1 wherein the reassigning is triggered by a number of write-erase cycles of the plurality of memory cells exceeding a predetermined number.

6. The adaptable method of claim 1 wherein the reassigning is triggered by a number of read operations directed to the plurality of memory cells exceeding a predetermined number.

7. The adaptable method of claim 1 wherein changing from the first mode to the second mode is triggered by elapse of a predetermined time.

8. The adaptable method of claim 1 wherein changing from the first mode to the second mode is triggered by environmental conditions exceeding predetermined criteria.

9. The adaptable method of claim 8 wherein the environmental conditions include temperature of the flash memory array and the predetermined criteria include a predetermined temperature which, when exceeded for a predetermined period of time, triggers the reassignment.

10. The adaptable method of claim 1 wherein changing from the first mode to the second mode is triggered by Error Correction Coding (ECC) statistics indicating that the plurality of memory cells have reduced data retention capability.

11. The adaptable method of claim 1 wherein the plurality of cells consists of all cells in a memory die.

12. The adaptable method of claim 1 wherein the plurality of cells consists of all cells in an erase block, the flash memory array containing other cells which continue to operate in the first mode while the plurality of cells operate in the second mode.

13. A nonvolatile memory array comprising:

a plurality of nonvolatile memory cells having three or more threshold voltage ranges individually assigned to represent logic states; and

programming circuits that in a first programming mode program the plurality of cells to a first two of the three or more threshold voltage ranges and that in a second programming mode program the plurality of cells to a second two of the three or more threshold voltage ranges, the second two including at least one threshold voltage range that is not included in the first two.

14. The nonvolatile memory array of claim 13 further comprising mode change circuit that triggers a change in the programming circuits from the first programming mode to the second programming mode in response to one or more predetermined criteria.

15. The nonvolatile memory array of claim 13 further comprising read circuits that read data programmed by the programming circuit in the first programming mode and the second programming mode.

16. The nonvolatile memory array of claim 15 wherein the read circuits distinguish between cells programmed to the first two of the three or more threshold voltage ranges using a discrimination voltage and distinguish between cells programmed to the second two of the three or more threshold voltage ranges using the same discrimination voltage.

17. An adaptable method of configuring a plurality of cells of a Multi-Level Cell (MLC) nonvolatile memory array comprising:

determining if the plurality of cells meet a first set of metrics for operation of MLC nonvolatile memory;

if the plurality of cells meet the first set of metrics, then configuring the plurality of cells to store more than one bit per cell using three or more predetermined threshold voltage ranges;

if the plurality of cells do not meet the first set of metrics, then configuring the plurality of cells to store one bit per cell using a first two of the three or more predetermined threshold voltage ranges; and

subsequently reconfiguring the plurality of cells to store one bit per cell using a second two of the three or more predetermined threshold voltage ranges.

18. The method of claim 17 wherein the configuring the plurality of cells to store one bit per cell includes setting a bit that indicates that the plurality of cells are to store one bit per cell and wherein subsequent access to the plurality of cells includes reading the bit to determine whether the plurality of cells store one bit per cell, or more than one bit per cell.

19. An adaptable method of operating a plurality of cells of an N state per cell Multi-Level Cell (MLC) nonvolatile memory array in different modes that use fewer than N states per cell, comprising:

configuring the N state per cell MLC nonvolatile memory for operation using fewer than N states by assigning M of the N cell states to represent M logical states, leaving M−

N of the N cell states unassigned, where M is less than N, in a first operating mode; and

subsequently reassigning at least one of the M logical states to one of the previously unassigned M−

N cell states.