SEMICONDUCTOR MEMORY DEVICE AND METHOD OF OPERATING THE SAME

• US 20140160846A1
• Filed: 03/14/2013
• Published: 06/12/2014
• Est. Priority Date: 12/11/2012
• Status: Active Grant

• Current Assignee: SK Hynix Inc.
• Original Assignee: SK Hynix Inc.
• Inventors: JANG, Yoon Soo, LEE, Jun Hyuk, LEE, Eun Joung, KIM, Seung Won
• Granted Patent: US 9,159,433 B2
• Time in Patent Office: Days
• US Class Current: 365/185.11
• CPC Class Codes: G11C 16/10 Programming or data input circuits
• CPC Class Codes: G11C 16/24 Bit-line control circuits
• CPC Class Codes: G11C 16/26 Sensing or reading circuits; Data output circuits

Abstract

A semiconductor memory device and a method of operating the same are disclosed. The semiconductor memory device includes a memory cell array including memory blocks, a voltage generator configured to generate a precharge voltage; and a read and write circuit coupled to the memory blocks through bit lines, and configured to supply the precharge voltage to the bit lines when a selected memory block is accessed. Here, the precharge voltage varies depending on a distance between the read and write circuit and the selected memory block.

Claims

1. A semiconductor memory device comprising:

a memory cell array including memory blocks;

a voltage generator configured to generate a precharge voltage; and

a read and write circuit coupled to the memory blocks through bit lines, and configured to supply the precharge voltage to the bit line when a selected memory block is accessed,

wherein the precharge voltage varies depending on a distance between the read and write circuit and the selected memory block.

2. The semiconductor memory device of claim 1, further comprising:

a voltage controller configured to control the voltage generator to adjust the precharge voltage based on a block address,

wherein the selected memory block is determined according to the block address.

3. The semiconductor memory device of claim 1, wherein the precharge voltage increases as the distance between the read and write circuit and the selected memory block increases, when a program operation is performed.

4. The semiconductor memory device of claim 1, wherein the precharge voltage reduces as the distance between the read and write circuit and the selected memory block increases, when a read operation is performed.

5. The semiconductor memory device of claim 1, further comprising:

an address decoder coupled to the memory blocks through word lines,

wherein the voltage generator generates further a read voltage and a read pass voltage in the read operation, and

the address decoder applies the read voltage to a word line selected from word lines coupled to the selected memory block and applies the read pass voltage to an unselected word line of the word lines coupled to the selected memory block.

6. The semiconductor memory device of claim 5, wherein the read voltage increases as the distance between the read and write circuit and the selected memory block increases, when the read operation is performed.

7. The semiconductor memory device of claim 5, wherein the read pass voltage increases as the distance between the read and write circuit and the selected memory block increases, when the read operation is performed.

8. The semiconductor memory device of claim 1, wherein voltages of the bit lines vary depending on data stored in selected memory cells of the selected memory block during an evaluation time, after the precharge voltage supplied to the bit line is blocked, and

the read and write circuit detects the data stored in the selected memory cells by sensing the voltages of the bit lines, after the evaluation time is elapsed.

9. The semiconductor memory device of claim 8, wherein the evaluation time increases as the distance between the read and write circuit and the selected memory block increases.

10. The semiconductor memory device of claim 8, wherein the read and write circuit further includes:

sensing transistors coupled between the bit lines and sensing nodes and configured to be turned on when a sensing signal is activated; and

latch units configured to detect the data stored in the selected memory cells according to voltages of the sensing nodes, and store the detected data,

and wherein a voltage of the activated sensing signal increases as the distance between the read and write circuit and the selected memory block increases.

11. A semiconductor memory device comprising:

a memory cell array including memory blocks, the memory blocks being divided into memory block groups;

a voltage generator configured to generate a precharge voltage; and

a read and write circuit coupled to the memory blocks through bit lines, and configured to supply the precharge voltage to the bit lines when a selected memory block is accessed,

wherein the precharge voltage varies depending on distance between a memory block group including the selected memory block and the read and write circuit.

12. The semiconductor memory device of claim 11, wherein the precharge voltage increases as the distance between the memory block group including the selected memory block and the read and write circuit increases, when a program operation is performed.

13. The semiconductor memory device of claim 11, wherein the precharge voltage reduces as the distance between the memory block group including the selected memory block and the read and write circuit increases, when a read operation is performed.

14. The semiconductor memory device of claim 13, further comprising:

an address decoder coupled to the memory blocks through word lines,

wherein the voltage generator generates further a read voltage and a read pass voltage in the read operation, and

the address decoder applies the read voltage to a word line selected from word lines coupled to the selected memory block and applies the read pass voltage to an unselected word line of the word lines coupled to the selected memory block.

15. The semiconductor memory device of claim 14, wherein the read voltage increases as the distance between the memory block group including the selected memory block and the read and write circuit increases, when the read operation is performed.

16. The semiconductor memory device of claim 14, wherein the read pass voltage increases as the distance between the memory block group including the selected memory block and the read and write circuit increases, when the read operation is performed.

17. A method of operating a semiconductor memory device including memory blocks coupled to a read and write circuit through bit lines, the method comprising:

receiving a command an address from an external device;

detecting a memory block selected from the memory blocks in response to a block address of the address;

generating a precharge voltage determined according to distance between the read and write circuit and the selected memory block; and

performing an operation corresponding to the command by supplying the precharge voltage to the bit lines.

18. The method of claim 17, wherein the command corresponds to a program operation, and the precharge voltage increases as the distance between the read and write circuit and the selected memory block increases.

19. The method of claim 17, wherein the command corresponds to a read operation, and the precharge voltage reduces as the distance between the read and write circuit and the selected memory block increases.

20. The method of claim 17, further comprising:

generating a read voltage and a read pass voltage,

wherein the read voltage is applied to a word line selected from word lines coupled to the selected memory block and the read pass voltage is applied to unselected word line of the word lines coupled to the selected memory block, when the operation corresponding to the command is performed, and

the read voltage and the read pass voltage increase as the distance between the read and write circuit and the selected memory block increases.