APPARATUSES AND METHODS TO CONTROL BODY POTENTIAL IN MEMORY OPERATIONS

• US 20140160851A1
• Filed: 12/06/2012
• Published: 06/12/2014
• Est. Priority Date: 12/06/2012
• Status: Active Grant

• Current Assignee: Micron Technology, Inc.
• Original Assignee: Micron Technology, Inc.
• Inventors: Zhao, Han, Goda, Akira, Parat, Krishna K., Mauri, Aurelio Giancarlo, Liu, Haitao, Tanzawa, Toru, Sakui, Koji, Yamada, Shigekazu
• Granted Patent: US 9,064,577 B2
• Time in Patent Office: Days
• US Class Current: 365/185.18
• CPC Class Codes: G11C 16/0483 comprising cells having several storage transistors connected in series
• CPC Class Codes: G11C 16/06 Auxiliary circuits, e.g. for writing into memory
• CPC Class Codes: G11C 16/08 Address circuits; Decoders; Word-line control circuits
• CPC Class Codes: G11C 16/16 for erasing blocks, e.g. arrays, words, groups
• CPC Class Codes: G11C 16/26 Sensing or reading circuits; Data output circuits
• CPC Class Codes: G11C 16/32 Timing circuits
• CPC Class Codes: G11C 16/3445 Circuits or methods to verify correct erasure of nonvolatile memory cells
• CPC Class Codes: G11C 16/3459 Circuits or methods to verify correct programming of nonvolatile memory cells
• CPC Class Codes: G11C 2213/71 Three dimensional array
• CPC Class Codes: G11C 8/08 Word line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, for word lines

Abstract

Some embodiments include apparatuses and methods having a memory cell string including memory cells located in different levels of the apparatus and a data line coupled to the memory cell string. The memory cell string includes a pillar body associated with the memory cells. At least one of such apparatus can include a module configured to store information in a memory cell among memory cells and/or to determine a value of information stored in a memory cell among memory cells. The module can also be configured to apply a voltage having a positive value to the data line and/or a source to control a potential of the body. Other embodiments are described.

Claims

1. An apparatus comprising:

a memory cell string including memory cells located in different levels of the apparatus, the memory cell string including a body associated with the memory cells;

a source coupled to the memory cell string;

a data line coupled to the memory cell string; and

a module configured to perform at least one of storing information in a memory cell among the memory cells and determining a value of information stored in a memory cell among the memory cells during a first time interval of the operation and to apply a voltage having a positive value to at least one of the source and the data line during a second time interval of the operation for controlling a potential of the body.

2. The apparatus of claim 1, wherein the module being configured to apply a voltage having a positive value to at least one of the source and the data line during a second time interval of the operation comprises the module being configured to induce drain leakage current in at least a portion of the body during the second time interval.

3. The apparatus of claim 1, wherein the module being configured to apply a voltage having a positive value to at least one of the source and the data line during a second time interval of the operation comprises the module being configured to inject holes into the body during the second time interval.

4. The apparatus of claim 1, wherein the module being configured to apply a voltage having a positive value to at least one of the source and the data line during a second time interval comprises the module being configured to apply a voltage having a positive value to the data line during the second time interval and to apply a voltage having a positive value to the source during the second time interval.

5. An apparatus comprising:

a memory cell string including memory cells and a select transistor located in different levels of the apparatus, the memory cell string including a body associated with the memory cells and the select transistor;

a control gate associated with the memory cell string;

a select gate associated with the select transistor;

a data line coupled to the body of memory cell string;

a source coupled to the body of memory cell string; and

a module configured to;

apply a first voltage having a positive value to the control gate in at least a portion of a first stage and in at least a portion of a second stage of an operation performed on a selected memory cell among the memory cells;

apply a second voltage having a first value in at least a portion of the first stage and a second value in at least a portion of the second stage to the select gate; and

apply a third voltage having a positive value to at least one of the data line and the source in at least a portion of the second stage.

6. The apparatus of claim 5, wherein the module is configured to store information in the selected memory cell in the first stage of the operation.

7. The apparatus of claim 5, wherein the module is configured to determine a value of information stored in the selected memory cell in the first stage of the operation.

8. The apparatus of claim 5, wherein the module is configured to determine whether a value of information stored in the selected memory cell reaches a target value in the first stage of the operation.

9. An apparatus comprising:

a memory cell string including memory cells and a select transistor located in different levels of the apparatus, the memory cell string including a body associated with the memory cells and the select transistor;

a control gate associated with the memory cell string;

a select gate associated with the select transistor;

a data line coupled to the body of memory cell string; and

a module configured to apply a voltage to the control gate in at least a portion of a first stage and in at least a portion of a second stage of an operation performed on one of the memory cells, apply a voltage having a first value in at least a portion of the first stage and a second value in at least a portion of the second stage to the select gate, and apply a voltage having a positive value to the data line in at least a portion of the second stage.

10. The apparatus of claim 9, wherein the module being configured to apply a voltage to the control gate in at least a portion of a first stage and in at least a portion of a second stage comprises the module being configured to apply a voltage have a program value in the at least a portion of the first stage and being configured to apply a ground potential to the control gate during the second stage.

11. The apparatus of claim 9, wherein the memory cell string further includes an additional select transistor associated with the body, and an additional select gate associated with the additional select transistor, and wherein the module is configured to apply an additional voltage to the additional select gate having a first value in at least a portion of the first stage and a second value in at least a portion of the second stage.

12. The apparatus of claim 9, wherein the first stage includes a write stage.

13. The apparatus of claim 9, wherein the first stage includes a read stage.

14. The apparatus of claim 9, wherein the first stage includes a write verify stage.

15. The apparatus of claim 9, wherein the first stage includes an erase verify stage.

16. A method comprising:

performing an operation on a memory cell among memory cells of a memory cell string of a device during a first time interval of the operation, the memory cells of the memory cell string located in different levels of the device, the memory cell string including a body associated with the memory cells and coupled to a data line and a source of the device; and

inducing drain leakage current in at least a portion of the body during a second time interval of the operation while a voltage on a control gate of the device associated the memory cell string has a positive value during at least a portion of the second time interval.

17. The method of claim 16, wherein performing the operation includes storing information in the memory cell.

18. The method of claim 16, wherein performing the operation includes determining a value of information stored in the memory cell.

19. The method of claim 16, wherein performing the operation includes determining whether a value of information stored in the memory cell reaches a target value.

20. The method of claim 16, wherein performing the operation during the first time interval includes applying a voltage having a first value during at least a portion of the first time interval to a select gate associated with a select transistor of the memory cell string;

and wherein inducing drain leakage current during a second time interval includes applying a voltage having a second value during at least a portion of the second time interval to the select gate, wherein the second value is less than the first value.

21. A method comprising:

storing information, during a first stage of an operation, in a selected memory cell among memory cells of a memory cell string, the memory cells of the memory cell string located in different levels of a device, the memory cell string including a body associated with the memory cells;

determining, during a second stage of the operation, whether a value of the information stored in the selected memory cell reaches a target value; and

applying a voltage having a positive value to at least one of a data line coupled to the memory cell string and a source coupled to the memory cell string during a time interval between the first and second stages to control a potential of the body.

22. The method of claim 21, wherein applying a voltage having a positive value to at least one of a data line coupled to the memory cell string and a source coupled to the memory cell string comprises applying a voltage having a positive value to the data line during the time interval and applying a voltage having a positive value to the source during the time interval.

23. The method of claim 21, further comprising:

applying a voltage having ground potential during the time interval to a control gate associated with the memory cell string.

24. The method of claim 21, further comprising:

applying a voltage having a positive value during at least a portion of the time interval to a control gate associated with the memory cell string.

25. The method of claim 21, further comprising:

removing excess electrons from the body before the first stage.

26. A method comprising:

determining, during a first time interval of an operation, a value of information stored in a selected memory among memory cells of a memory cell string, the memory cells of the memory cell string located in different levels of a device, the memory cell string including a body associated with the memory cells; and

applying a voltage having a positive value to at least one of a data line coupled to the memory cell string and a source coupled to the memory cell string during a second time interval of the operation to control a potential of the body.

27. The method of claim 26, wherein applying a voltage having a positive value to at least one of a data line coupled to the memory cell string and a source coupled to the memory cell string during a second time interval of the operation to control a potential of the body comprises applying a voltage having a positive value to the data line during the second time interval and applying a voltage having a positive value to the source during the second time interval.

28. The method of claim 26, further comprising:

applying a voltage having ground potential to a control gate associated with the memory cell string during the second time interval.

29. The method of claim 26, further comprising:

applying a voltage having a positive value to a control gate associated with the memory cell string during at least a portion of the second time interval.

30. A method comprising:

performing an operation on a memory cell among memory cells of a memory cell string during a first stage of the operation, the memory cells of the memory cell string located in different levels of a device, the memory cell string including a body associated with the memory cells;

applying a voltage having a positive value to a data line coupled to the body during at least a portion of a second stage of the operation; and

applying a voltage having a positive value to a source coupled to the body during at least a portion of the second stage of the operation.

31. The method of claim 30, wherein performing an operation during the first stage comprises applying a first voltage during at least a portion of the first stage to a select gate associated with a select transistor of the memory cell string, the method further comprising:

applying a second voltage during at least a portion of the second stage to the select gate, wherein the second voltage has a value less than a value of the first voltage.

32. The method of claim 31, wherein performing an operation during the first stage further comprises applying a third voltage during at least a portion of the first stage to an additional select gate associated with an additional select transistor of the memory cell string, the method further comprising applying a fourth voltage during at least a portion of the second stage to the additional select gate, wherein the fourth voltage has a value less than a value of the third voltage.

33. The method of claim 32, further comprising:

decreasing the voltage on the select gate and the additional select gate to zero volts by the end of the second stage.

34. The method of claim 30, further comprising:

holding a control gate associated with the memory cell string at a positive value at the end of the second stage.