Method of Maintaining the State of Semiconductor Memory Having Electrically Floating Body Transistor
4 Assignments
0 Petitions
Accused Products
Abstract
Methods of maintaining a state of a memory cell without interrupting access to the memory cell are provided, including applying a back bias to the cell to offset charge leakage out of a floating body of the cell, wherein a charge level of the floating body indicates a state of the memory cell, and accessing the cell.
-
Citations
49 Claims
-
1-29. -29. (canceled)
-
30. A semiconductor memory cell comprising:
-
a floating body region configured to be charged to a level indicative of a state of the memory cell; a first region in electrical contact with said floating body region, located at a surface of said floating body region; and a second region in electrical contact with said floating body region, located below said floating body region, configured to inject charge into said floating body region to maintain said state of the memory cell; wherein an amount of charge injected into said floating body is a function of a charge stored in said floating body region. - View Dependent Claims (31, 32, 33, 34, 35, 36, 37)
-
-
38. A semiconductor memory array comprising:
-
a plurality of semiconductor memory cells arranged in a matrix of rows and columns, wherein each said semiconductor memory cell includes; a floating body region configured to be charged to a level indicative of a state of the memory cell; a first region in electrical contact with said floating body region; a second region in electrical contact with said floating body region and spaced apart from said first region; and a gate positioned between said first and second regions; wherein a back-bias region is commonly connected to at least two of said memory cells, and when a first memory cell of said at least two of said memory cells is in a first state and a second memory cell of said at least two of said memory cells is in a second state, application of a bias via said back-bias region maintains said first memory cell in said first state and said second memory cell in said second state. - View Dependent Claims (39, 40, 41, 42, 43, 44, 45)
-
-
46. A semiconductor memory cell comprising:
a bipolar device having a floating base region, a collector, and an emitter, wherein; a state of said memory cell is stored in said floating base region, said collector is located below said floating base region; said state of said memory cell is maintained through a back-bias applied to said collector. - View Dependent Claims (47, 48, 49)
Specification