APPARATUS AND SYSTEM FOR REAL-TIME EXECUTION OF ULTRASOUND SYSTEM ACTIONS

• US 20140160895A1
• Filed: 12/05/2013
• Published: 06/12/2014
• Est. Priority Date: 12/06/2012
• Status: Active Grant

• Current Assignee: White Eagle Sonic Technologies, Inc.
• Original Assignee: White Eagle Sonic Technologies, Inc.
• Inventors: Tobias, Richard, Wu, Bicheng, Parikh, Ashish
• Granted Patent: US 9,983,905 B2
• Time in Patent Office: Days
• US Class Current: 367/137
• CPC Class Codes: B06B 1/0207 Driving circuits specially adapted for particular applications, see the relevant subclass, e.g. G01; circuits for steering transducer arrays G10K11/34; basic circuits H03
• CPC Class Codes: G06F 9/4843 by program, e.g. task dispatcher, supervisor, operating system

Abstract

Apparatus for real-time execution of ultrasound system actions includes processor and memory to store instructions. Execution of the instructions causes processor to receive a task list including task actions that include next task action in task list. Next task action includes task instructions. Processor determines whether next task instruction in next task action is a timed instruction that includes a timestamp field having a time value indicating a time at which next task action is to be executed, and a hardware-enable field indicating hardware elements required to be available before execution of timed instruction. If next task instruction is not a timed instruction, processor may execute next task instruction. If next task instruction is timed instruction, processor determines whether time value has expired. If time value has expired, processor signals an error has occurred, and if time value has not expired, processor waits for time value. Other embodiments are described.

Claims

1. An apparatus for real-time execution of ultrasound system actions comprising:

a processor; and

a memory to store instructions, which when executed by the processor, causes the processor to;

receive a task list including a plurality of task actions, the plurality of task actions includes a next task action in the task list, wherein each of the task actions includes a plurality of task instructions;

determine whether a next task instruction included in the next task action is a timed instruction, wherein the timed instruction includes a timestamp field and a hardware-enable field,

wherein the timestamp field includes a time value indicating a time at which the next task action is to be executed,

wherein the hardware-enable field indicates hardware elements that need to be available before execution of the timed instruction,

when the processor determines that the next task instruction is not a timed instruction, execute the task instruction, and when the processor determines that the task instruction is a timed instruction, determine whether the time value has expired, and

signal an error has occurred when the processor determines that the time value has expired, and wait for the time value when the processor determines that the time value has not expired.

2. The apparatus of claim 1, wherein the memory to further store instructions, which when executed by the processor, causes the processor to:

read from the memory a halt bit after signaling the error;

halt processing the task list when the halt bit is set, and continue processing the next task action when the halt bit is not set.

3. The apparatus of claim 1, wherein, when the processor determines that the time has not expired and waits for the time value, the memory to further store instructions, which when executed by the processor, causes the processor to:

determine whether the hardware elements that are indicated in the hardware-enable field are available, and

execute the next task instruction when the hardware elements are available.

4. The apparatus of claim 3, wherein, when the processor determines that the hardware elements are not available, the memory to further store instructions, which when executed by the processor, causes the processor to:

determine whether the next task instruction is a soft timing constraint or a hard timing constraint, and

signal an error when the next task instruction is determined to be a hard timing constraint and waiting for the hardware elements to become available when the next task instruction is determined to be a soft timing constraint.

5. The apparatus of claim 4, wherein, when the next task instruction is determined to be a soft timing constraint, the memory to further store instructions, which when executed by the processor, causes the processor to:

stall a global clock timer.

6. The apparatus of claim 1, wherein determining whether the time value has expired includes comparing the time value to a time indicated on a global clock.

7. The apparatus of claim 3, further comprising:

a beamer coupled to the processor, to generate signals,

wherein the processor executing the next task instruction includes signaling to the beamer to generate signals.

8. The apparatus of claim 7, further comprising:

a probe interface coupled to the beamer, the probe interface to transmit the signals to at least one probe unit and to receive signals from the at least one the probe unit.

9. The apparatus of claim 8, further comprising:

a receiver coupled to the processor and the probe interface, the receiver to receive and process the signals received from the probe interface.

10. The apparatus of claim 7, wherein the signals cause the probe units to fire their beams, respectively.

11. The apparatus of claim 10, wherein the beams include at least one of ultrasound beams or laser beams.

12. The apparatus of claim 1, wherein, when the next task instruction is determined to be a non timing instruction, the memory to further store instructions, which when executed by the processor, causes the processor to:

change a value of a global clock timer.

13. A system for real-time execution of ultrasound system actions comprising:

at least one probe unit,

an input device to receive a task list inputted by a user;

an adaptive scheduler including;

a processor, and

a memory to store instructions, which when executed by the processor, causes the processor to;

receive a task list including a plurality of task actions, the plurality of task actions includes a next task action in the task list, wherein each of the task actions includes a plurality of task instructions,

determine whether a next task instruction included in the next task action is a timed instruction, wherein the timed instruction includes a timestamp field and a hardware-enable field,

wherein the timestamp field includes a time value indicating a time at which the next task instruction is to be executed,

wherein the hardware-enable field indicates hardware elements that need to be available before execution of the timed instruction.

when the processor determines that the next task instruction is not a timed instruction, execute the next task instruction, and when the processor determines that the next task instruction is a timed instruction, determine whether the time value has expired, and

signal an error has occurred when the processor determines that the time value has expired, and wait for the time value when the processor determines that the time value has not expired.

14. The system of claim 13, wherein the memory to further store instructions, which when executed by the processor, causes the processor to:

read from the memory a halt bit after signaling the error;

halt processing the task list when the halt bit is set, and continue processing the next task instruction when the halt bit is not set.

15. The system of claim 13, wherein, when the processor determines that the time has not expired and waits for the time value, the memory to further store instructions, which when executed by the processor, causes the processor to:

determine whether the hardware elements that are indicated in the hardware-enable field are available, and

execute the next task instruction when the hardware elements are available.

16. The system of claim 15, wherein, when the processor determines that the hardware elements are not available, the memory to further store instructions, which when executed by the processor, causes the processor to:

determine whether the next task instruction is a soft timing constraint or a hard timing constraint, and

signal an error when the next task instruction is determined to be a hard timing constraint and waiting for the hardware elements to become available when the next task instruction is determined to be a soft timing constraint.

17. The system of claim 16, wherein, when the next task instruction is determined to be a soft timing constraint, the memory to further store instructions, which when executed by the processor, causes the processor to:

stall a global clock timer.

18. The system of claim 13, wherein determining whether the time value has expired includes comparing the time value to a time indicated on a global clock.

19. The system of claim 15, wherein the adaptive scheduler further comprises:

a beamer coupled to the processor, to generate signals, wherein the processor executing the next task instruction includes signaling to the beamer to generate signals;

a probe interface coupled to the beamer, the probe interface to transmit the signals to the at least one probe unit and to receive signals from the at least one the probe unit; and

a receiver coupled to the processor and the probe interface, the receiver to receive and process the signals received from the probe interface.

20. The system of claim 19, further comprising:

an imager to generate display signals based on the data signals received from the receiver and to transmit the display signals to a display that displays at least one of;

images based on the display signals, texts based on the display signals, or video based on the display signals.

21. A method for real-time execution of ultrasound system actions comprising:

receiving by an electronic circuit included in an adaptive scheduler a task list including a plurality of task actions, the plurality of task actions includes a next task action in the task list, wherein each of the task actions includes a plurality of task instructions;

determining by the electronic circuit whether a next task instruction included in the next task action is a timed instruction, wherein the timed instruction includes a timestamp field and a hardware-enable field,

wherein the timestamp field includes a time value indicating a time at which the next task action is to be executed,

wherein the hardware-enable field indicates hardware elements that need to be available before execution of the timed instruction,

when the electronic circuit determines that the next task instruction is not a timed instruction, execute the task instruction, and when the electronic circuit determines that the task instruction is a timed instruction, determine whether the time value has expired, and

signaling by the electronic circuit an error has occurred when the electronic circuit determines that the time value has expired, and wait for the time value when the electronic circuit determines that the time value has not expired.

22. The method of claim 21, further comprising:

reading by the electronic circuit from the memory a halt bit after signaling the error;

halting by the electronic circuit processing the task list when the halt bit is set, and continue processing the next task action when the halt bit is not set.

23. The method of claim 21, further comprising, when the electronic circuit determines that the time has not expired and waits for the time value,:

determining by the electronic circuit whether the hardware elements that are indicated in the hardware-enable field are available, and

executing by the electronic circuit the next task instruction when the hardware elements are available.

24. The method of claim 23, further comprising, when the processor determines that the hardware elements are not available:

determining by the electronic circuit whether the next task instruction is a soft timing constraint or a hard timing constraint, and

signaling by the electronic circuit an error when the next task instruction is determined to be a hard timing constraint and waiting for the hardware elements to become available when the next task instruction is determined to be a soft timing constraint.

25. The method of claim 24, further comprising, when the next task instruction is determined to be a soft timing constraint:

stalling by the electronic circuit a global clock timer.