PRODUCTION METHOD FOR A SUSPENDED STRUCTURE COMPONENT AND A TRANSISTOR CO-INTEGRATED ON A SAME SUBSTRATE

• US 20140162392A1
• Filed: 12/05/2013
• Published: 06/12/2014
• Est. Priority Date: 12/06/2012
• Status: Active Grant

• Current Assignee: Commissariat a L'Energie Atomique (AES Corporation)
• Original Assignee: Commissariat a L'Energie Atomique (AES Corporation)
• Inventors: Ollier, Eric, Arcamone, Julien, Savoye, Mylene
• Granted Patent: US 9,193,582 B2
• Time in Patent Office: Days
• US Class Current: 438/50
• CPC Class Codes: B81C 1/0019 Flexible or deformable structures not provided for in groups B81C1/00142 - B81C1/00182
• CPC Class Codes: B81C 1/00246 Monolithic integration, i.e. micromechanical structure and electronic processing unit are integrated on the same substrate
• CPC Class Codes: B81C 2203/0728 Pre-CMOS, i.e. forming the micromechanical structure before the CMOS circuit
• CPC Class Codes: B81C 2203/0771 Stacking the electronic processing unit and the micromechanical structure
• CPC Class Codes: H01L 27/0617 comprising components of the field-effect type H01L27/0251 takes precedence
• CPC Class Codes: H01L 27/1203 the substrate comprising an insulating body on a semiconductor body, e.g. SOI three-dimensional layout H01L27/0688

Abstract

A method of forming a microelectronic device comprising, on a same substrate, at least one electro-mechanical component provided with a suspended structure and at least one transistor, the method comprising a step of release of the suspended structure from the electromechanical component after having formed metal interconnection levels of components.

Claims

1-13. -13. (canceled)

14. A Method of forming a microelectronic device comprising, on a same substrate comprising a semi-conducting layer, at least one component provided with at least one suspended structure and at least one transistor, the method comprising the steps consisting in:

a) forming in a first region of the semi-conducting layer one or more sacrificial blocks arranged on either side or around at least one given block of said semi-conducting layer intended to form at least one portion of a suspended structure of said component and one or more electrical insulating block(s) of the component, the sacrificial blocks and the insulating blocks being formed by;

forming openings in said semi-conducting layer then,

filling the openings with at least one dielectric material, one or several first opening(s) being filled with dielectric material so as to form said sacrificial blocks, one or several second opening(s) being filled with dielectric material so as to form one or more electrical insulating block(s) of the component, the second opening(s) filled with dielectric material forming an insulating closed contour around said component,

b) forming a transistor from a second region of said semi-conducting layer,

c) forming one or more interconnection levels in at least one insulating layer arranged on said semi-conducting layer,

d) forming at least one cavity in the insulating layer so as to reveal at least partially said given block intended to form at least one part of suspended structure and so as to reveal at least partially the sacrificial blocks on either side of said given semi-conducting block,

e) removing in said cavity said sacrificial blocks and a sacrificial layer around said given semi-conducting block so as to release said given block forming the suspended structure.

15. The method according to claim 14, wherein the step e) of removal is carried out by etching and wherein, between step d) and step e), a protective layer is formed covering the sides and the bottom of the cavity, an opening then being made in said protective layer so as to reveal said given semi-conducting block and said sacrificial blocks arranged on either side of said semi-conducting block, the protective layer protecting the insulating layer(s) of the connection levels at step e).

16. The method according to claim 15, wherein the sacrificial blocks are based on a dielectric material, the protective layer being based on a material resistant to said etching of said dielectric material and to an etching of the sacrificial layer arranged under said revealed part of said given block carried out at step e).

17. The method according to claim 14, wherein the cavity formed at step d) comprises sloping sides with respect to a normal to the principal plane of the substrate.

18. The method according to claim 17, wherein the openings are formed through a stop layer resting on the semi-conducting layer, the method further comprising, after filling the openings with the dielectric material, a step of removal of dielectric material extending beyond the mouth of the openings by planarization until the stop layer is reached.

19. The method according to claim 14, wherein the formation of the electrical connection levels comprises the formation of an electrical connection conducting line between the electro-mechanical component and the electronic component passing above one of the insulating blocks separating and isolating the electro-mechanical component and the electronic component.

20. The method according to claim 14, wherein after step a) and prior to step c), doped zones are formed in the first region and the second region of the semi-conducting layer, the method further comprising a step of activation annealing of the dopants in doped zones of the first region and of said second region.

21. The method according to claim 14, wherein the semi-conducting layer is based on monocrystalline silicon.

22. The method according to claim 14, wherein the sacrificial layer is an insulating layer of a semi-conductor on isolator substrate, said insulating layer being intercalated between a semi-conducting support layer and the semi-conducting layer.

23. The method according to claim 14, wherein the filling of the first opening(s) is carried out by means of a dielectric material different to the dielectric material for filling the second opening(s).

24. The method according to claim 14, wherein the first opening(s) have a profile different to that of the second opening(s), the second opening(s) comprising sloping sides with respect to a normal to the principal plane of the substrate.

25. The method according to claim 14, wherein at step d) for forming the cavity, the insulating blocks are entirely covered by the insulating layer, the insulating blocks being entirely conserved at step e) of removal of the sacrificial blocks in said cavity.

26. The method according to claim 14, wherein at step d) of forming the cavity the insulating blocks are partially revealed by the insulating cavity, the insulating blocks being partially conserved at step e) of removal of the sacrificial blocks in said cavity, a portion of the insulating closed contour around said component being at the end of step e) formed of a portion of the second openings wherein the dielectric material for filling the second openings has been conserved during step d) and of a portion of the second openings wherein the dielectric material for filling the second openings has been removed during step d).