FLEXIBLE SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME

• US 20140162406A1
• Filed: 06/17/2013
• Published: 06/12/2014
• Est. Priority Date: 12/07/2012
• Status: Active Grant

• Current Assignee: Samsung Electronics Co. Ltd.
• Original Assignee: Samsung Electronics Co. Ltd.
• Inventors: CHO, Eun-hyoung, CHOI, Jun-hee, SOHN, Jin-seung
• Granted Patent: US 8,889,442 B2
• Time in Patent Office: Days
• US Class Current: 438/110
• CPC Class Codes: H01L 21/568 Temporary substrate used as encapsulation process aid H01L21/4832 and H01L21/566 take precedence
• CPC Class Codes: H01L 21/6835 using temporarily an auxiliary support
• CPC Class Codes: H01L 2221/6835 used as a support during build up manufacturing of active devices
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
• CPC Class Codes: Y02E 10/50 Photovoltaic [PV] energy

Abstract

Provided is a method of transferring semiconductor elements formed on a non-flexible substrate to a flexible substrate. Also, provided is a method of manufacturing a flexible semiconductor device based on the method of transferring semiconductor elements. A semiconductor element grown or formed on the substrate may be efficiently transferred to the resin layer while maintaining an arrangement of the semiconductor elements. Furthermore, the resin layer acts as a flexible substrate supporting the vertical semiconductor elements.

Claims

1. A method of transferring semiconductor elements, the method comprising:

forming a plurality of vertical semiconductor elements on a substrate;

forming an inorganic insulating layer on a surface of each of the plurality of vertical semiconductor elements and attaching an OH group on a surface of the inorganic insulating layer;

forming an amphipathic layer on the surface of the inorganic insulating layer;

applying a polymerizable composition on top of the plurality of vertical semiconductor elements coated with the amphipathic layer;

curing the applied polymerizable composition thereby converting the applied polymerizable composition into a resin layer such that the plurality of vertical semiconductor elements are embedded in the resin layer;

separating the resin layer along with the plurality of vertical semiconductor elements from the substrate; and

etching a portion of the resin layer such that an upper portion of each of the plurality of vertical semiconductor elements is exposed.

2. The method of claim 1, wherein the substrate is a crystalline substrate.

3. The method of claim 1, wherein the substrate is an amorphous substrate.

4. The method of claim 1, wherein a surface of the substrate is coated by at least one of an underlayer, a buffer layer, and a mask layer, and the plurality of vertical semiconductor elements are formed on the at least one of the underlayer, the buffer layer, and the mask layer.

5. The method of claim 4, wherein the surface of the substrate is coated by the underlayer comprising at least one of titanium, hafnium, zirconium, and aluminum.

6. The method of claim 4, wherein the surface of the substrate is coated by the buffer layer, and the buffer layer is a group III-V compound semiconductor.

7. The method of claim 4, wherein surface of the substrate is coated by the buffer layer comprising one of a GaN-based semiconductor, an AIN-based semiconductor, and a combination thereof.

8. The method of claim 4, wherein the surface of the substrate is coated by the buffer layer comprising at least one of GaN, AN, InGaN, AlGaN, and AlInGaN.

9. The method of claim 4, wherein, the surface of the substrate is coated by the buffer layer, and the method further comprises patterning the buffer layer.

10. The method of claim 4, wherein the surface of the substrate is coated by the mask layer, and a thickness of the mask layer is about 10 nm to about 500 nm.

11. The method of claim 4, wherein the surface of the substrate is coated by the mask layer, and a thickness of the mask layer is about 10 nm to about 200 nm.

12. The method of claim 1, wherein the plurality of vertical semiconductor elements each have one of a pyramid shape and a rod shape.

13. The method of claim 1, wherein the plurality of vertical semiconductor elements comprise a group III-V compound semiconductor.

14. The method of claim 1, wherein the plurality of vertical semiconductor elements are a GaN-based semiconductor.

15. The method of claim 1, wherein the plurality of vertical semiconductor elements comprise at least one of GaN, InGaN, AlGaN, and AlInGaN.

16. The method of claim 1, wherein the inorganic insulating layer is SiO₂.

17. The method of claim 1, wherein the inorganic insulating layer is treated with plasma or a strong acid.

18. The method of claim 1, wherein the amphipathic layer has a methoxysilyl group as a hydrolizable group.

19. The method of claim 1, wherein the amphipathic layer has an epoxide group as an organofunctional group.

20. The method of claim 1, wherein the amphipathic layer comprises a silane coupling agent.

21. The method of claim 1, wherein the amphipathic layer comprises a 3-glycidoxypropyltrimethoxysilane.

22. The method of claim 1, wherein the polymerizable composition comprises a polymerizable monomer;

a reactive diluent; and

an initiator.

23. The method of claim 22, wherein the polymerizable monomer is urethane acrylate.

24. The method of claim 22, wherein the reactant diluent is 2-hydroxypropyl-acrylate.

25. The method of claim 22, wherein the initiator is 1-hydroxycyclohexyl phenyl ketone

26. The method of claim 1, wherein a bonding strength between the cured resin layer and the plurality of vertical semiconductor elements is stronger than a bonding strength between the substrate and the plurality of vertical semiconductor elements.

27. The method of claim 1, wherein the etching the resin layer comprises using an etching gas including CF₄ and O₂.

28. The method of claim 1, wherein etching the resin layer thereby exposing an upper portion of the vertical semiconductor elements is performed before separating the resin layer along with the vertical semiconductor elements from the substrate.

29. A method of transferring semiconductor elements, the method comprising:

forming a plurality of vertical semiconductor elements on a substrate;

forming an inorganic insulating layer on a surface of each of the plurality of vertical semiconductor elements and attaching an OH group on a surface of the inorganic insulating layer;

forming an amphipathic layer on a surface of the inorganic insulating layer;

applying a polymerizable composition on top of the vertical semiconductor elements coated with the amphipathic layer;

compressing a support layer on the applied polymerizable composition;

curing the applied polymerizable composition thereby converting the applied polymerizable composition into a resin layer such that the plurality of vertical semiconductor elements are embedded in the resin layer;

separating the support layer, along with the resin layer and the plurality of vertical semiconductor elements, from the substrate;

removing the support layer; and

etching a portion of the resin layer such that an upper portion of each of the plurality of vertical semiconductor elements is exposed.

30. The method of claim 29, wherein the support layer is a polyethylene terephthalate film.

31. The method of claim 29, wherein a surface of the support layer contacting the applied polymerizable composition is coated with an adhesion promoter.

32. The method of claim 29, wherein a surface of the support layer contacting the applied polymerizable composition is coated with an adhesion preventer.

33. The method of claim 29, wherein a bonding strength between the resin layer and the support layer is stronger than a bonding strength between the substrate and the plurality of vertical semiconductor elements.

34. The method of claim 29, wherein the removing the support layer comprises etching.

35. The method of claim 29, wherein the removing the support layer comprises using a photolysis process to destroy a bond between the support layer and the resin layer.

36. A method of manufacturing a flexible semiconductor element, the method comprising:

preparing a flexible laminate comprising;

a resin layer;

a plurality of vertical semiconductor elements embedded in the resin layer, wherein an upper portion of each of the plurality of vertical semiconductor elements is exposed above the resin layer, and a bottom portion of each of the plurality of vertical semiconductor elements is exposed below the resin layer;

forming an upper electrode on an upper surface of the flexible laminate, wherein the upper electrode is electrically connected to the plurality of vertical semiconductor elements; and

forming a bottom electrode electrically on a bottom surface of the flexible laminate, wherein the bottom electrode is electrically connected to the plurality of vertical semiconductor elements.

37. The method of claim 36, wherein the flexible laminate further comprises at least one of a mask layer, a buffer layer, and an underlayer disposed below the plurality of vertical semiconductor elements.