VECTOR EXECUTION UNIT WITH PRENORMALIZATION OF DENORMAL VALUES

• US 20140164465A1
• Filed: 03/11/2013
• Published: 06/12/2014
• Est. Priority Date: 12/06/2012
• Status: Active Grant

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: Muff, Adam J., Schardt, Paul E., Shearer, Robert A., Tubbs, Matthew R.
• Granted Patent: US 9,092,257 B2
• Time in Patent Office: Days
• US Class Current: 708/501
• CPC Class Codes: G06F 15/8053 Vector processors
• CPC Class Codes: G06F 2207/3828 Multigauge devices, i.e. capable of handling packed numbers without unpacking them
• CPC Class Codes: G06F 5/012 in floating-point computations
• CPC Class Codes: G06F 7/483 Computations with numbers represented by a non-linear combination of denominational numbers, e.g. rational numbers, logarithmic number system or floating-point numbers G06F7/4806, G06F7/4824, G06F7/49, G06F7/491, G06F7/544 take precedence
• CPC Class Codes: G06F 7/49936 Normalisation mentioned as feature only
• CPC Class Codes: G06F 7/5443 Sum of products for applications thereof, see the relevant places, e.g. G06F17/10, H03H17/00

Abstract

A method, circuit arrangement, and program product for executing instructions including denormal values for one or more operands in a vector execution unit. A denormal value operand may be prenormalized by a first processing lane of the vector execution unit upon detecting the denormal value. The prenormalized value and any other operands of the instruction may be communicated to a dot product adder of the vector execution unit. The dot product adder performs at least a portion of the floating point operation with the prenormalized value and any other operands of the instruction.

Claims

1. A circuit arrangement, comprising:

a vector execution unit configured to execute a floating point instruction to perform a floating point operation using at least one operand identified by the instruction, wherein at least one operand of the floating point instruction is a denormal value, the vector execution unit comprising;

a first processing lane configured to prenormalize the denormal value operand loaded in the first processing lane, and

a dot product adder configured to perform the floating point operation using the prenormalized value.

2. The circuit arrangement of claim 1, wherein the vector execution unit further comprises an instruction pipeline, and the vector execution unit is configured to monitor the instruction pipeline to detect a floating point instruction including a denormal value for an operand in the instruction pipeline and flag the detected floating point instruction in the instruction pipeline.

3. The circuit arrangement of claim 1, wherein the floating point instruction includes the denormal value operand and a second operand,

wherein the dot product adder includes a first input and a second input, the first processing lane is connected to the first input of the dot product adder,

the vector execution unit further comprises a second processing lane connected to the second input of the dot product adder,

the vector execution unit further comprises multiplexing logic connected between the first processing lane and the second input of the dot product adder, and the first processing lane is further configured to:

load the denormal value operand and the second operand for processing,

communicate the second operand to the second input of the dot product adder through the multiplexing logic such that the second operand bypasses the first processing lane, and

communicate the prenormalized value to the first input of the dot product adder.

4. The circuit arrangement of claim 1, wherein the floating point instruction corresponds to a floating point addition operation.

5. The circuit arrangement of claim 1, wherein the floating point instruction corresponds to a floating point subtraction operation.

6. The circuit arrangement of claim 1, wherein the floating point instruction corresponds to a floating point multiplication addition operation.

7. The circuit arrangement of claim 6, wherein the floating point instruction includes the denormal value operand, a second operand, and a third operand,

wherein the dot product adder includes a first input and a second input, the first processing lane includes floating point multiplication logic and is connected to the first input of the dot product adder,

the vector execution unit further comprises a second processing lane connected to the second input of the dot product adder,

the vector execution unit further comprises multiplexing logic connected between the first processing lane and the second input of the dot product adder, and the first processing lane is further configured to:

load the denormal value operand, the second operand, and the third operand for processing,

perform a floating point multiplication operation with the second operand and the third operand to generate a floating point result with the floating point multiplication logic of the first processing lane,

communicate the floating point result to the second input of the dot product adder through the multiplexing logic, and

communicate the prenormalized value to the first input of the dot product adder,

wherein the dot product adder performs the floating point operation using the prenormalized value by performing a dot product addition operation with the floating point result and the prenormalized value.

8. The circuit arrangement of claim 1, wherein the first processing lane prenormalizes the denormal value and the dot product adder performs the floating point operation in a single pass of an execution pipeline of the vector execution unit.

9. The circuit arrangement of claim 1, wherein the first processing lane prenormalizes the denormal value and the dot product adder performs the floating point operation without reissuing the floating point instruction.

10. The circuit arrangement of claim 1, wherein the floating point instruction is a first floating point instruction, the floating point operation is a first floating point operation, and the first processing lane is further configured to perform a second floating point operation for a second floating point instruction that includes exclusively normal value operands.

11. An integrated circuit device comprising the circuit arrangement of claim 1.

12. A program product comprising a computer readable medium and logic definition program code resident on the computer readable medium and defining the circuit arrangement of claim 1.